UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 283

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

(3) Baud rate generator control register 0 (BRGC0)
Address: FF71H After reset: 1FH R/W
BRGC0
Note Note the following points when selecting the TM50 output as the base clock.
Symbol
This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter.
BRGC0 can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 1FH.
It is not necessary to enable the TO50 pin as a timer output pin in any mode.
Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation
(TMC501 = 1).
PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty =
50%.
MDL04
TPS01
TPS01
7
0
0
1
1
0
0
0
0
1
1
1
1
1
1
Figure 13-4. Format of Baud Rate Generator Control Register 0 (BRGC0)
MDL03
TPS00
TPS00
6
0
1
0
1
0
1
1
1
1
1
1
1
1
1
CHAPTER 13 SERIAL INTERFACE UART0
TM50 output
f
f
f
PRS
PRS
PRS
MDL02
/2
/2
/2
5
0
0
0
0
0
0
1
1
1
1
3
5
User’s Manual U17504EJ2V0UD
Note
MDL04
MDL01
1 MHz
250 kHz
62.5 kHz
f
PRS
4
0
0
1
1
1
0
0
1
1
= 2 MHz
Base clock (f
MDL03
MDL00
3
0
1
0
0
1
0
1
0
1
2.5 MHz
625 kHz
156.25 kHz
f
PRS
= 5 MHz
XCLK0
10
26
27
28
29
30
31
k
8
9
MDL02
) selection
2
Setting prohibited
f
f
f
f
f
f
f
f
f
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
5 MHz
1.25 MHz
312.5 kHz
f
PRS
Selection of 5-bit counter
/8
/9
/10
/26
/27
/28
/29
/30
/31
= 10 MHz
MDL01
output clock
1
10 MHz
2.5 MHz
625 kHz
f
PRS
= 20 MHz
MDL00
0
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