UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 439

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

<R>
(5)
Clock output selection register (CKS)
CKS enables/disables the clock output (PCL) to the LCD controller/driver, and sets the output clock.
CKS is set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets CKS to 00H.
Note
Cautions 1. Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0).
Remarks 1. f
Address: FF40H
Symbol
CKS
mode register 14 (PM14)).
Enabling/disabling the PCL clock output is specified by combining the PM140 settings (see (7) Port
2. Bits 5 to 7 must be set to 0.
2. f
Other than above
Other than above
PRS
SUB
CLOE
CCS3
: Peripheral hardware clock oscillation frequency
: Subsystem clock oscillation frequency
7
0
1
0
0
1
Figure 17-9. Format of Clock Output Selection Register
After reset: 00H
PM140
CCS2
6
0
0
1
1
0
CHAPTER 17 LCD CONTROLLER/DRIVER
Clock output to LCD controller/driver enabled
Clock output to LCD controller/driver disabled
R/W
CCS1
User’s Manual U17504EJ2V0UD
5
0
1
1
0
Specification of enable/disable for clock output
CLOE
CCS0
4
0
1
0
to LCD controller/driver
f
f
f
Setting prohibited
PRS
PRS
SUB
CCS3
/2
/2
3
6
7
32.768 kHz
32.768 kHz
PCL output clock selection
f
SUB
-
CCS2
=
2
156.25 kHz 312.5 kHz
78.125 kHz 156.25 kHz
Note
10 MHz
f
PRS
CCS1
=
1
-
20 MHz
f
CCS0
PRS
0
=
437