UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 280
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UPD78F0386GK-8EU-A
Manufacturer Part Number
UPD78F0386GK-8EU-A
Description
MCU 96KB FLASH 5KB RAM
Manufacturer
Renesas Electronics America
Series
78K0/Lx2r
Datasheet
1.UPD78F0372GK-8EU-A.pdf
(624 pages)
Specifications of UPD78F0386GK-8EU-A
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LCD, LVD, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
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13.3 Registers Controlling Serial Interface UART0
(1) Asynchronous serial interface operation mode register 0 (ASIM0)
278
Address: FF70H After reset: 01H R/W
Serial interface UART0 is controlled by the following five registers.
Notes 1.
Symbol
ASIM0
This 8-bit register controls the serial communication operations of serial interface UART0.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 01H.
Asynchronous serial interface operation mode register 0 (ASIM0)
Asynchronous serial interface reception error status register 0 (ASIS0)
Baud rate generator control register 0 (BRGC0)
Port mode register 1 (PM1)
Port register 1 (P1)
Figure 13-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (1/2)
2.
The input from the R
Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0),
and receive buffer register 0 (RXB0) are reset.
POWER0
POWER0
RXE0
TXE0
0
<7>
Note 1
1
0
1
0
1
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit
Enables operation of the internal operation clock.
Disables transmission (synchronously resets the transmission circuit).
Enables transmission.
Disables reception (synchronously resets the reception circuit).
Enables reception.
TXE0
<6>
X
D0 pin is fixed to high level when POWER0 = 0.
CHAPTER 13 SERIAL INTERFACE UART0
RXE0
<5>
User’s Manual U17504EJ2V0UD
Enables/disables operation of internal operation clock
Note 2
.
PS01
4
Enables/disables transmission
Enables/disables reception
PS00
3
CL0
2
SL0
1
0
1
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