UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 62

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

(3) Stack pointer (SP)
60
(b) Zero flag (Z)
(c) Register bank select flags (RBS0 and RBS1)
(d) Auxiliary carry flag (AC)
(e) In-service priority flag (ISP)
(f) Carry flag (CY)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area.
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from
the stack memory.
Each stack operation saves/restores data as shown in Figures 3-15 and 3-16.
Caution Since reset signal generation makes the SP contents undefined, be sure to initialize the SP
SP
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction
execution is stored.
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-
level vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H)
(see 19.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) can not be acknowledged.
Actual request acknowledgement is controlled by the interrupt enable flag (IE).
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
SP15 SP14 SP13 SP12 SP11 SP10 SP9
before using the stack.
15
Figure 3-14. Format of Stack Pointer
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17504EJ2V0UD
SP8
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
0