UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 323

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

(e) Normal reception
R
X
D6 (input)
Reception is enabled and the R
interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
The 8-bit counter of the baud rate generator starts counting when the falling edge of the R
detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the
R
as a start bit.
When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift
register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt
(INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun
error (OVE6) occurs, however, the receive data is not written to RXB6.
Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception
position of the stop bit, and a reception error interrupt (INTSR6/INTSRE6) is generated on completion of
reception.
Cautions 1. If a reception error occurs, read ASIS6 and then RXB6 to clear the error flag. Otherwise,
INTSR6
X
RXB6
D6 pin input is sampled again (
2. Reception is always performed with the “number of stop bits = 1”. The second stop bit
3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6)
an overrun error will occur when the next data is received, and the reception error
status will persist.
is ignored.
before reading RXB6.
Figure 14-19. Reception Completion Interrupt Request Timing
Start
D0
CHAPTER 14 SERIAL INTERFACE UART6
D1
X
D6 pin input is sampled when bit 7 (POWER6) of asynchronous serial
in Figure 14-19). If the R
User’s Manual U17504EJ2V0UD
D2
D3
D4
D5
X
D6 pin is low level at this time, it is recognized
D6
D7
Parity
Stop
X
D6 pin input is
321