ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 147

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.2.4
13.2.5
7728G–AVR–06/10
SPI Status Register – SPSR
SPI Data Register – SPDR
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI
is in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first read-
ing the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL
set, and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the ATtiny87/167 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the
SPI is in Master mode (see
CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at
f
The SPI interface on the ATtiny87/167 is also used for program memory and EEPROM down-
loading or uploading. See
verification.
• Bits 7:0 - SPD7:0: SPI Data
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the reg-
ister causes the Shift Register Receive buffer to be read.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
clkio
/4 or lower.
SPD7
SPIF
R/W
R
7
X
7
0
WCOL
SPD6
R/W
X
R
6
6
0
Table
“Serial Downloading” on page 238
SPD5
R/W
13-4). This means that the minimum SCK period will be two
5
X
R
5
–
0
SPD4
R/W
X
4
R
4
–
0
SPD3
R/W
X
3
R
3
–
0
ATtiny87/ATtiny167
SPD2
R/W
2
X
R
2
–
0
for serial programming and
SPD1
R/W
X
1
R
1
–
0
SPD0
SPI2X
R/W
R/W
X
0
0
0
SPDR
Undefined
SPSR
147