ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 91

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.5.1
10.5.2
10.5.3
10.6
7728G–AVR–06/10
Compare Match Output Unit
Force Output Compare
Compare Match Blocking by TCNT0 Write
Using the Output Compare Unit
The OCR0A Register is double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCR0A
Compare Register to either top or bottom of the counting sequence. The synchronization pre-
vents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output
glitch-free.
The OCR0A Register access may seem complex, but this is not case. When the double buff-
ering is enabled, the CPU has access to the OCR0A Buffer Register, and if double buffering is
disabled the CPU will access the OCR0A directly.
In non-PWM waveform generation modes, the match output of the comparator can be forced
by writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not
set the OCF0A flag or reload/clear the timer, but the OC0A pin will be updated as if a real com-
pare match had occurred (the COM0A1:0 bits settings define whether the OC0A pin is set,
cleared or toggled).
All CPU write operations to the TCNT0 Register will block any compare match that occurs in
the next timer clock cycle, even when the timer is stopped. This feature allows OCR0A to be
initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter
clock is enabled.
Since writing TCNT0 in any mode of operation will block all compare matches for one timer
clock cycle, there are risks involved when changing TCNT0 when using the Output Compare
channel, independently of whether the Timer/Counter is running or not. If the value written to
TCNT0 equals the OCR0A value, the compare match will be missed, resulting in incorrect
waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the
counter is downcounting.
The setup of the OC0A should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC0A value is to use the Force Output Com-
pare (FOC0A) strobe bit in Normal mode. The OC0A Register keeps its value even when
changing between Waveform Generation modes.
Be aware that the COM0A1:0 bits are not double buffered together with the compare value.
Changing the COM0A1:0 bits will take effect immediately.
The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Generator
uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next compare
match. Also, the COM0A1:0 bits control the OC0A pin output source.
simplified schematic of the logic affected by the COM0A1:0 bit setting. The I/O Registers, I/O
bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control
registers (DDR and PORT) that are affected by the COM0A1:0 bits are shown. When referring
to the OC0A state, the reference is for the internal OC0A Register, not the OC0A pin.
ATtiny87/ATtiny167
Figure 10-4
shows a
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