ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 280

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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ATtiny87/ATtiny167
3. ‘Disable Clock Source’ command remains enabled.
4. Comparison between ADC inputs and voltage references.
5. Register bits of DIDR1.
In the Dynamic Clock Switch module, the ‘Disable Clock Source’ command remains run-
ning after disabling the targeted clock source (the clock source is set in the CLKSELR
register).
Problem fix / workaround.
After a ‘Disable Clock Source’ command, reset the CLKCSR register writing 0x80.
Code example:
; (*) !!! At this moment, if any other clock source is selected by
CLKSELR,
;
; ==> WORKAROUND ...
In the Analog Comparator module, comparing any ADC input (ADC[10..0]) with voltage
references (2.56V, 1.28V, 1.10V, 0.64V or 0.32V) fails.
Regardless, AIN1 input can be compared with the voltage references and any ADC input
can be compared with AIN0 input.
Problem fix / workaround.
Do not use this configuration.
ADC8D, ADC9D and ADC10D (Digital Input Disable) initially located at bit 4 up to 6 are
instead located at bit 0 up to 2. These register bits are also in write only mode.
Problem fix / workaround.
Allow for the change in bit locations and the access mode restriction.
; Select crystal oscillator
; Disable clock source (crystal oscillator)
ldi
sts
ldi
ldi
sts
sts
sts
this clock source will also stop !!!
temp1,(0x0F<<CSEL0)
CLKSELR, temp1
temp2,(1<<CLKCCE)
temp3,(0x01<<CLKC0)
CLKCSR,temp2
CLKCSR,temp3
CLKCSR,temp2
; CSEL = "0001"
; Enable CLKCSR register access
; (*) Disable crystal oscillator clock
7728G–AVR–06/10