ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 155

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.3.5
7728G–AVR–06/10
Start Condition Detector
Referring to the timing diagram
If the Slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the Master does a read operation it must terminate the operation by force the
acknowledge bit low after the last byte transmitted.
Figure 14-6. Start Condition Detector, Logic Diagram
The start condition detector is shown in Figure 14-6. The SDA line is delayed (in the range of
50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only
enabled in Two-wire mode.
The start condition detector is working asynchronously and can therefore wake up the proces-
sor from the Power-down sleep mode. However, the protocol used might have restrictions on
the SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time
set by the CKSEL Fuses (see
taken into the consideration. Refer to the USISIF bit description on page 157 for further
details.
1. The a start condition is generated by the Master by forcing the SDA low line while the
2. In addition, the start detector will hold the SCL line low after the Master has forced an
3. The Master set the first bit to be transferred and releases the SCL line (C). The Slave
4. After eight bits are transferred containing slave address and data direction (read or
5. If the Slave is addressed it holds the SDA line low during the acknowledgment cycle
6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is
SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift
Register, or by setting the corresponding bit in the PORT Register to zero. Note that
the USI Data Register bit must be set to one for the output to be enabled. The slave
device’s start detector logic (Figure 14-6.) detects the start condition and sets the
USISIF Flag. The flag can generate an interrupt if necessary.
negative edge on this line (B). This allows the Slave to wake up from sleep or com-
plete its other tasks before setting up the USI Data Register to receive the address.
This is done by clearing the start condition flag and reset the counter.
samples the data and shift it into the USI Data Register at the positive edge of the
SCL clock.
write), the Slave counter overflows and the SCL line is forced low (D). If the slave is
not the one the Master has addressed, it releases the SCL line and waits for a new
start condition.
before holding the SCL line low again (i.e., the Counter Register must be set to 14
before releasing SCL at (D)). Depending of the R/W bit the Master or Slave enables
its output. If the bit is set, a master read operation is in progress (i.e., the slave drives
the SDA line) The slave can hold the SCL line low after the acknowledge (E).
given by the Master (F). Or a new start condition is given.
Write( USISIF)
SDA
SCL
“Clock Systems and their Distribution” on page
(Figure
14-5), a bus transfer involves the following steps:
D Q
CLR
ATtiny87/ATtiny167
D Q
CLR
USISIF
CLOCK
HOLD
24) must also be
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