TDA5230 Infineon Technologies, TDA5230 Datasheet - Page 82

• Manufacturer Part Number: TDA5230
• Description: IC RECEIVER ASK/FSK 28-TSSOP
• Manufacturer: Infineon Technologies
• Type: Receiverr

Specifications of TDA5230

• Package / Case: 28-TSSOP
• Frequency: 433MHz ~ 450MHz, 865MHz ~ 868MHz
• Sensitivity: -111dBm
• Data Rate - Maximum: 20 kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Current - Receiving: 8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Operating Frequency: 870 MHz
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: SP000076520; TDA5230; TDA5230INTR

Figure 40
AD Converter:
The AD sampling rate division factor ADCDIV is always a multiple of 16 times of the data
rate, and in a range from 96 kHz to 320 kHz. For example for a 2 kb/s data rate the ADC
sampling rate has to be a multiple of 32 kHz, the optimal ADC sampling rate is 320 kHz.
Because of f
Therefore, there is an ideal sample rate (e.g. 320 kHz) and finally a real sample rate
(322.576 kHz, note: values slightly higher than 320 kHz are tolerated if calculated by the
IAF Tool). The difference between the ideal and the real sample rate should not be more
than 2%. For better performance, the highest possible ADC sampling rate should be set.
For data rates lower or equal to 1.1kb/s a maximum sample rate of 120 kHz should be
selected.
A data decimation is required to correct the values which are dependent on the factor of
oversampling.
The calculation formulas for ADCDIV / ASKDEC factors:
The following calculations are fully supported by the IAF TDA523x Configuration
Tool!
Data Sheet
Demodulator
Generator
RSSI-
from
FSK-
from
SYS
AD-Control and Matched-FIlter
A
and the used clock divider, not all ADC sampling rates are possible.
D
Detector
Peak
Slicer
Pre
Master-Control-Unit
from
EoC
SoC
RSSI-Track
RSSI-Clear
f
sys
Clock-Generation
78
Control-Unit
Filter
CIC
A/D
EOM
T
nom
/ 16
Functional Description
T
nom
Dif
Version 4.0, 2007-06-01
/ 16
unsliced data
at rate T
nom
TDA523x
/ 16
to
signal
detection