OM13006,598 NXP Semiconductors, OM13006,598 Datasheet
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UM10415 EM773 User manual Rev. 1 — 10 September 2010 Document information Info Content Keywords Energy metering, ARM Cortex-M0, EM773 Abstract EM773 User manual User manual ...
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... NXP Semiconductors Revision history Rev Date Description 1 <tbd> Initial version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: UM10415 User manual salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 September 2010 ...
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UM10415 Chapter 1: EM773 Introductory information Rev. 1 — 10 September 2010 1.1 Introduction The EM773 is an ARM Cortex-M0 based, low-cost 32-bit energy metering IC, designed for 8/16-bit smart metering applications. The EM773 offers programmability and on-chip metrology functionality ...
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... NXP Semiconductors • Serial interfaces: – UART with fractional baud rate generation, internal FIFO, and RS-485 support. – One SPI controller with SSP features and with FIFO and multi-protocol capabilities. 2 – I C-bus interface supporting full I data rate of 1 Mbit/s with multiple address recognition and monitor mode. ...
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... NXP Semiconductors 1.4 Block diagram EM773 system bus slave HIGH-SPEED GPIO ports GPIO PIO0/1/2/3 RXD TXD UART DTR, CTS, RTS CT32B0_MAT[2:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP0 CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP0 Fig 1. EM773 block diagram UM10415 User manual Chapter 1: EM773 Introductory information ...
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... NXP Semiconductors 1.5 ARM Cortex-M0 processor The ARM Cortex-M0 processor is described in detail in Cortex-M0 processor and core processor core is configured as follows: • System options: – The Nested Vectored Interrupt Controller (NVIC) is included and supports interrupts. – The system tick timer is included. • ...
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UM10415 Chapter 2: EM773 Memory mapping Rev. 1 — 10 September 2010 2.1 Memory map Figure 2 shows the memory and peripheral address space of the EM773. The AHB peripheral area size and is divided to ...
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... NXP Semiconductors EM773 4 GB reserved AHB peripherals reserved APB peripherals 1 GB reserved 0.5 GB reserved 16 kB boot ROM reserved 8 kB SRAM reserved 32 kB on-chip flash 0 GB Fig 2. EM773 memory map UM10415 User manual 0xFFFF FFFF 16-127 reserved 12-15 0x5020 0000 8-11 0x5000 0000 ...
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UM10415 Chapter 3: EM773 System configuration Rev. 1 — 10 September 2010 3.1 Introduction The system configuration block controls oscillators, start logic, and clock generation of the EM773. Also included in this block are registers for setting the priority for ...
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... NXP Semiconductors IRC oscillator watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator SYSTEM PLL system oscillator SYSPLLCLKSEL (system PLL clock select) Fig 3. EM773 CGU block diagram 3.4 Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. ...
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... NXP Semiconductors Table 3. Register overview: system control block (base address 0x4004 8000) Name Access Address offset Description SYSRSTSTAT R 0x030 - - 0x034 - 0x03C SYSPLLCLKSEL R/W 0x040 SYSPLLCLKUEN R/W 0x044 - - 0x048 - 0x06C MAINCLKSEL R/W 0x070 MAINCLKUEN R/W 0x074 SYSAHBCLKDIV R/W 0x078 - - 0x07C SYSAHBCLKCTRL R/W ...
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... NXP Semiconductors Table 3. Register overview: system control block (base address 0x4004 8000) Name Access Address offset Description PDRUNCFG R/W 0x238 - - 0x23C - 0x3F0 DEVICE_ID R 0x3F4 3.4.1 System memory remap register The system memory remap register selects whether the ARM interrupt vectors are read from the boot ROM, the flash, or the SRAM ...
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... NXP Semiconductors 3.4.3 System PLL control register This register connects and enables the system PLL and configures the PLL multiplier and divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources. The input frequency is multiplied high frequency, then divided down to provide the actual clock used by the CPU, peripherals, and memories ...
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... NXP Semiconductors Table 8. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit description Bit Symbol 1 FREQRANGE 31:2 - 3.4.6 Watchdog oscillator control register This register configures the watchdog oscillator. The oscillator consists of an analog and a digital part. The analog part contains the oscillator function and generates an analog clock (Fclkana) ...
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... NXP Semiconductors Table 9. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit description Bit Symbol 31:9 - 3.4.7 Internal resonant crystal control register This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset and written by the boot code on start-up. Table 10. ...
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... NXP Semiconductors 3.4.8 System reset status register The SYSRSTSTAT register shows the source of the latest reset event. The bits are cleared by writing a one to any of the bits. The POR event clears all other bits in this register, but if another reset signal - for example EXTRST - remains asserted after the POR signal is negated, then its bit is set to detected ...
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... NXP Semiconductors 3.4.10 System PLL clock source update enable register This register updates the clock source of the system PLL with the new input clock after the SYSPLLCLKSEL register has been written to. In order for the update to take effect, first write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN. ...
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... NXP Semiconductors Table 15. Main clock source update enable register (MAINCLKUEN, address 0x4004 8074) bit description Bit Symbol 0 ENA 31:1 - 3.4.13 System AHB clock divider register This register divides the main clock to provide the system clock to the core, memories, and the peripherals. The system clock can be shut down completely by setting the DIV bits to 0x0 ...
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... NXP Semiconductors Table 17. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description Bit Symbol 3 FLASHREG 4 FLASHARRAY 5 I2C 6 GPIO 7 CT16B0 8 Metrology engine clock 9 CT32B0 10 CT32B1 11 SSP0 12 UART 13 Metrology engine clock WDT UM10415 User manual Chapter 3: EM773 System configuration …continued Value Description Enables clock for flash register interface ...
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... NXP Semiconductors Table 17. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description Bit Symbol 16 IOCON 31:19 - 3.4.15 SPI0 clock divider register This register configures the SPI0 peripheral clock SPI0_PCLK. The SPI0_PCLK can be shut down by setting the DIV bits to 0x0. ...
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... NXP Semiconductors Table 20. WDT clock source select register (WDTCLKSEL, address 0x4004 80D0) bit description Bit Symbol 1:0 SEL 31:2 - 3.4.18 WDT clock source update enable register This register updates the clock source of the watchdog timer with the new input clock after the WDTCLKSEL register has been written to ...
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... NXP Semiconductors Table 23. CLKOUT clock source select register (CLKOUTCLKSEL, address 0x4004 80E0) bit description Bit Symbol 1:0 SEL 31:2 - 3.4.21 CLKOUT clock source update enable register This register updates the clock source of the CLKOUT pin with the new clock after the CLKOUTCLKSEL register has been written to ...
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... NXP Semiconductors Table 26. POR captured PIO status registers 0 (PIOPORCAP0, address 0x4004 8100) bit description Bit Symbol 11:0 CAPPIO0_11 to CAPPIO0_0 23:12 CAPPIO1_11 to CAPPIO1_0 31:24 CAPPIO2_7 to CAPPIO2_0 3.4.24 POR captured PIO status register 1 The PIOPORCAP1 register captures the state (HIGH or LOW) of the PIO pins of port 2 (PIO2_8 to PIO2_11) and port 3 at power-on-reset ...
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... NXP Semiconductors Table 28. BOD control register (BODCTRL, address 0x4004 8150) bit description Bit Symbol 3:2 BODINTVAL 4 BODRSTENA 31:5 - 3.4.26 System tick counter calibration register Table 29. System tick timer calibration register (SYSTCKCAL, address 0x4004 8158) bit description Bit Symbol 25:0 CAL 31: ...
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... NXP Semiconductors 3.4.28 Start logic signal enable register 0 This STARTERP0 register enables or disables the start signal bits in the start logic. The bit assignment is identical to Table 31. Start logic signal enable register 0 (STARTERP0, address 0x4004 8204) bit description Bit Symbol 10:0 ERPIO0_10 to ERPIO0_0 31: ...
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... NXP Semiconductors 3.4.31 Deep-sleep mode configuration register This register controls the behavior of the WatchDog (WD) oscillator and the BOD circuit when the device enters Deep-sleep mode. This register must be initialized at least once before entering Deep-sleep mode with one of the four values shown in Table 34 ...
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... NXP Semiconductors Remark: Reserved bits in this register must always be written as indicated. This register must be initialized correctly before entering Deep-sleep mode. Table 35. Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit description Bit Symbol 2 BOD_PD 5 WDTOSC_PD 7 - 10:8 - 12:11 - 31:13 - 3.4.32 Wake-up configuration register The bits in this register determine the state the chip enters when it is waking up from Deep-sleep mode ...
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... NXP Semiconductors Table 36. Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit description Bit Symbol 4 METENG_PD 5 SYSOSC_PD 6 WDTOSC_PD 7 SYSPLL_PD 15:13 - 31:16 - 3.4.33 Power-down configuration register The bits in the PDRUNCFG register control the power to the various analog blocks. This register can be written to at any time while the chip is running, and a write will take effect immediately with the exception of the power-down signal to the IRC ...
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... NXP Semiconductors Table 37. Power-down configuration register (PDRUNCFG, address 0x4004 8238) bit description Bit Symbol 1 IRC_PD 2 FLASH_PD 3 BOD_PD 4 METENG_PD 5 SYSOSC_PD 6 WDTOSC_PD 7 SYSPLL_PD 15:13 - 31:16 - 3.4.34 Device ID register This device ID register is a read-only register and contains the part ID for the EM773. This register is also read by the ISP/IAP commands Table 38 ...
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... NXP Semiconductors 3.5 Reset Reset has four sources on the EM773: the RESET pin, Watchdog Reset, Power-On Reset (POR), and Brown Out Detect (BOD). In addition, there is a software reset. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once ...
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... NXP Semiconductors 3.7.1.1 Power configuration in Active mode Power consumption in Active mode is determined by the following configuration choices: • The SYSAHBCLKCTRL register controls which memories and peripherals are running • The power to various analog blocks (PLL, oscillators, the BOD circuit, and the flash ...
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... NXP Semiconductors 3.7.2.3 Wake-up from Sleep mode Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns to its original power configuration defined by the contents of the PDRUNCFG and the SYSAHBCLKDIV registers ...
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... NXP Semiconductors external pin is used for wake-up, enable and clear the wake-up pin in the start logic registers 5. In the SYSAHBCLKCTRL register counter/timer or WDT if needed. 6. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register 7. Use the ARM WFI instruction. 3.7.3.3 Wake-up from Deep-sleep mode The microcontroller can wake up from Deep-sleep mode in the following ways: • ...
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... NXP Semiconductors 3. Store data to be retained in the general purpose registers 4. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register 5. Ensure that the IRC is powered by setting bits IRCOUT_PD and IRC_PD to zero in the PDRUNCFG register before entering Deep power-down mode. 6. Use the ARM WFI instruction. ...
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... NXP Semiconductors 1. Configure the port pin as match output in the IOCONFIG block. Select from pins PIO0_1 or PIO0_8 to PIO0_11, which are inputs to the start logic and also hold a match output function the corresponding counter/timer, set the match value, and configure the match output for the selected pin. ...
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... NXP Semiconductors create the output clock(s), or are sent directly to the output(s). The main output clock is then divided the programmable feedback divider to generate the feedback clock. The output signal of the phase-frequency detector is also monitored by the lock detector, to signal when the PLL has locked on to the input clock. ...
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... NXP Semiconductors Table 39. PLL frequency parameters Parameter FCLKIN FCCO FCLKOUT P M 3.9.4.1 Normal mode In normal mode the post divider is enabled, giving a 50% duty cycle clock with the following frequency relations: To select the appropriate values for M and recommended to follow these steps: 1. Specify the input clock frequency Fclkin. ...
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... NXP Semiconductors 3.10 Flash memory access Depending on the system clock frequency, access to the flash memory can be configured with various access times by writing to the FLASHCFG register at address 0x4003 C010. This register is part of the flash configuration block (see Remark: Improper setting of this register may result in incorrect operation of the EM773 flash memory ...
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UM10415 Chapter 4: EM773 PMU (Power Management Unit) Rev. 1 — 10 September 2010 4.1 Introduction The PMU controls the Deep power-down mode. Four general purpose register in the PMU can be used to retain data during Deep power-down mode. ...
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... NXP Semiconductors Table 43. Power control register (PCON, address 0x4003 8000) bit description Bit Symbol 11 DPDFLAG 31:12 - 4.2.2 General purpose registers The general purpose registers retain data through the Deep power-down mode when power is still applied to the V Only a “cold” boot when all power has been completely removed from the chip will reset the general purpose registers ...
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UM10415 Chapter 5: EM773 Interrupt controller Rev. 1 — 10 September 2010 5.1 Introduction The Nested Vectored Interrupt Controller (NVIC integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient ...
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... NXP Semiconductors Table 46. Connection of interrupt sources to the Vectored Interrupt Controller Exception Number UM10415 User manual Vector Function Flag(s) Offset UART Rx Line Status (RLS) Transmit Holding Register Empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) End of Auto-Baud (ABEO) Auto-Baud Time-Out (ABTO) ...
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UM10415 Chapter 6: EM773 I/O Configuration Rev. 1 — 10 September 2010 6.1 How to read this chapter The implementation of the I/O configuration registers varies for different EM773 parts and packages. 6.2 Introduction The I/O configuration registers control the ...
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... NXP Semiconductors 6.3.1 Pin function The FUNC bits in the IOCON registers can be set to GPIO (FUNC = 000 peripheral function. If the pins are GPIO pins, the GPIOnDIR registers determine whether the pin is configured as an input or output (see the pin direction is controlled automatically depending on the pin’s functionality. The GPIOnDIR registers have no effect for peripheral functions ...
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... NXP Semiconductors Each port pin PIOn_m has one IOCON register assigned to control the pin’s function and electrical characteristics. Some input functions (SCK0, DSR0, DCD0, and RI0) are multiplexed to several physical pins. The IOCON_LOC registers select the pin location for each of these functions. ...
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... NXP Semiconductors Table 47. Register overview: I/O configuration (base address 0x4004 4000) Name Access IOCON_PIO1_6 R/W IOCON_PIO1_7 R/W IOCON_SCK_LOC R/W Table 48. I/O configuration registers ordered by port number Port pin PIO0_0 PIO0_1 PIO0_2 PIO0_3 PIO0_4 PIO0_5 PIO0_6 PIO0_7 PIO0_8 PIO0_9 PIO0_10 PIO1_1 PIO1_2 ...
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... NXP Semiconductors Table 49. IOCON_PIO2_0 register (IOCON_PIO2_0, address 0x4004 4008) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - Table 50. IOCON_nRESET_PIO0_0 register (IOCON_nRESET_PIO0_0, address 0x4004 400C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - UM10415 User manual ...
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... NXP Semiconductors Table 51. IOCON_PIO0_1 register (IOCON_PIO0_1, address 0x4004 4010) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - Table 52. IOCON_PIO1_8 register (IOCON_PIO1_8, address 0x4004 4014) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - UM10415 User manual ...
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... NXP Semiconductors Table 53. IOCON_PIO0_2 register (IOCON_PIO0_2, address 0x4004 401C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - Table 54. IOCON_PIO0_3 register (IOCON_PIO0_3 address 0x4004 402C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - UM10415 User manual ...
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... NXP Semiconductors Table 55. IOCON_PIO0_4 register (IOCON_PIO0_4 address 0x4004 4030) bit description Bit Symbol 2:0 FUNC 7:3 9:8 I2CMODE 31:10 - [1] Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000). Table 56. IOCON_PIO0_5 register (IOCON_PIO0_5 address 0x4004 4034) bit description ...
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... NXP Semiconductors Table 57. IOCON_PIO1_9 register (IOCON_PIO1_9 address 0x4004 4038) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - Table 58. IOCON_PIO3_4 register (IOCON_PIO3_4, address 0x4004 403C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - UM10415 User manual ...
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... NXP Semiconductors Table 59. IOCON_PIO3_5 register (IOCON_PIO3_5, address 0x4004 4048) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - Table 60. IOCON_PIO0_6 register (IOCON_PIO0_6 address 0x4004 404C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - UM10415 User manual ...
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... NXP Semiconductors Table 61. IOCON_PIO0_7 register (IOCON_PIO0_7, address 0x4004 4050) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - Table 62. IOCON_PIO0_8 register (IOCON_PIO0_8, address 0x4004 4060) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - UM10415 User manual ...
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... NXP Semiconductors Table 63. IOCON_PIO0_9 register (IOCON_PIO0_9, address 0x4004 4064) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - Table 64. IOCON_SWCLK_PIO0_10 register (IOCON_SWCLK_PIO0_10, address 0x4004 4068) bit description Bit Symbol Value 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - UM10415 User manual ...
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... NXP Semiconductors Table 65. IOCON_R_PIO1_1 register (IOCON_R_PIO1_1, address 0x4004 407C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS UM10415 User manual Value Description Selects pin function. 000 Selects function R. This function is reserved. Select one of the alternate functions below. 001 Selects function PIO1_1. ...
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... NXP Semiconductors Table 66. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2, address 0x4004 4080) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS Table 67. IOCON_SWDIO_PIO1_3 register (IOCON_SWDIO_PIO1_3, address 0x4004 4090) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:8 - UM10415 User manual Value Description Selects pin function. ...
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... NXP Semiconductors Table 68. IOCON_PIO1_4 register (IOCON_PIO1_4, address 0x4004 4094) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:8 - [1] This pin functions as WAKEUP pin if the EM773 is in Deep power-down mode regardless of the value of FUNC. UM10415 User manual Value Description [1] Selects pin function. ...
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... NXP Semiconductors Table 69. IOCON_PIO1_11 register (IOCON_PIO1_11 address 0x4004 4098) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:8 - Table 70. IOCON_PIO3_2 register (IOCON_PIO3_2, address 0x4004 409C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - UM10415 User manual Value Description Selects pin function ...
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... NXP Semiconductors Table 71. IOCON_PIO1_5 register (IOCON_PIO1_5, address 0x4004 40A0) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - Table 72. IOCON_PIO1_6 register (IOCON_PIO1_6, address 0x4004 40A4) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - UM10415 User manual ...
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... NXP Semiconductors Table 73. IOCON_PIO1_7 register (IOCON_PIO1_7, address 0x4004 40A8) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 7:6 - 31:8 - 6.4.2 IOCON location registers The IOCON location registers are used to select a physical pin for multiplexed functions. Remark: Note that once the pin location has been selected, the function still must be configured in the corresponding IOCON registers for the function to be usable on that pin ...
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UM10415 Chapter 7: EM773 Pin configuration Rev. 1 — 10 September 2010 7.1 How to read this chapter The EM773 is available in HVQFN33. Table 75. EM773 pin configurations Part EM773 7.2 Pin configuration terminal 1 index area PIO2_0/DTR RESET/PIO0_0 ...
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... NXP Semiconductors 7.3 EM773 Pin description Table 76. UM10415 pin description table (HVQFN33 package) Symbol Pin Start logic input PIO0_0 to PIO0_10 [2] RESET/PIO0_0 2 yes [3] PIO0_1/CLKOUT/ 3 yes CT32B0_MAT2 [3] PIO0_2/SSEL0/ 8 yes CT16B0_CAP0 [3] PIO0_3 9 yes [4] PIO0_4/SCL 10 yes [4] PIO0_5/SDA 11 yes [3] PIO0_6/SCK0 15 yes [3] PIO0_7/CTS 16 yes [3] PIO0_8/MISO0/ 17 yes CT16B0_MAT0 ...
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... NXP Semiconductors Table 76. UM10415 pin description table (HVQFN33 package) Symbol Pin Start logic input [3] SWCLK/PIO0_10/SCK0/ 19 yes CT16B0_MAT2 [5] I_HIGHGAIN 21 no PIO1_1 to PIO1_9; PIO1_11 [5] VOLTAGE 22 no [5] R/PIO1_1 CT32B1_MAT0 [5] R/PIO1_2 CT32B1_MAT1 [5] SWDIO/PIO1_3 CT32B1_MAT2 PIO1_4 CT32B1_MAT3/WAKEUP [3] PIO1_5/RTS CT32B0_CAP0 [3] PIO1_6/RXD CT32B0_MAT0 [3] PIO1_7/TXD CT32B0_MAT1 [3] PIO1_8 7 no [3] PIO1_9 ...
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... NXP Semiconductors Table 76. UM10415 pin description table (HVQFN33 package) Symbol Pin Start logic input PIO1_11 27 no PIO2_0 [3] PIO2_0/DTR 1 no PIO3_0 to PIO3_5 no [3] PIO3_2 28 no [3] PIO3_4 13 no [3] PIO3_5 [6] XTALIN 4 - [6] XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled inactive, no pull-up/down enabled. ...
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UM10415 Chapter 8: EM773 General Purpose I/O (GPIO) Rev. 1 — 10 September 2010 8.1 How to read this chapter The number of GPIO pins available on each port depends on the EM773 part and the package. See Table 77. ...
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... NXP Semiconductors Table 78. Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000; port 3: 0x5003 0000) …continued Name Access GPIOnRIS R GPIOnMIS R GPIOnIC 8.3.1 GPIO data register The GPIOnDATA register holds the current logic state of the pin (HIGH or LOW), independently of whether the pin is configured as an GPIO input or output or as another digital function ...
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... NXP Semiconductors The rules show that the pins mirror the current logic level. Therefore floating pins may drive an unpredictable level when switched from input to output. 8.3.2 GPIO data direction register Table 80. GPIOnDIR register (GPIO0DIR, address 0x5000 8000 to GPIO3DIR, address 0x5003 8000) bit description ...
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... NXP Semiconductors 8.3.5 GPIO interrupt event register Table 83. GPIOnIEV register (GPIO0IEV, address 0x5000 800C to GPIO3IEV, address 0x5003 800C) bit description Bit Symbol 11:0 IEV 31:12 - 8.3.6 GPIO interrupt mask register Bits set to HIGH in the GPIOnIE register allow the corresponding pins to trigger their individual interrupts and the combined GPIOnINTR line ...
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... NXP Semiconductors 8.3.8 GPIO masked interrupt status register Bits read HIGH in the GPIOnMIS register reflect the status of the input lines triggering an interrupt. Bits read as LOW indicate that either no interrupt on the corresponding input pins has been generated or that the interrupt is masked. GPIOMIS is the state of the interrupt after masking ...
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... NXP Semiconductors If the address bit (i+2) associated with the GPIO port bit 11 written is HIGH, the value of the GPIODATA register bit i is updated. If the address bit (i+2) is LOW, the corresponding GPIODATA register bit i is left unchanged. GPIODATA register at address + 0x098 Fig 7. Masked write operation to the GPIODATA register ...
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... NXP Semiconductors Read operation If the address bit associated with the GPIO data bit is HIGH, the value is read. If the address bit is LOW, the GPIO data bit is read as 0. Reading a port DATA register yields the state of port pins 11:0 ANDed with address bits 13:2. ...
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UM10415 Chapter 9: EM773 Universal Asynchronous Transmitter (UART) Rev. 1 — 10 September 2010 9.1 How to read this chapter The UART block is identical for all EM773 parts. 9.2 Basic configuration The UART is configured using the following registers: ...
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... NXP Semiconductors 9.5 Clocking and power control The UART block is gated by the AHBCLKCTRL register (see UART clock, which is used by the UART baud rate generator, is controlled by the UARTCLKDIV register (see The UART_PCLK can be disabled in the UARTCLKDIV register (see UART block can be disabled through the System AHB clock control register bit 12 (see Table 17) for power savings ...
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... NXP Semiconductors Table 89. Register overview: UART (base address: 0x4000 8000) Name Access Address Description offset U0TER R/W 0x030 Transmit Enable Register. Turns off UART transmitter for use with software flow control 0x034 - Reserved 0x048 U0RS485CTRL R/W 0x04C RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes ...
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... NXP Semiconductors 9.6.1 UART Receiver Buffer Register (U0RBR - 0x4000 8000, when DLAB = 0, Read Only) The U0RBR is the top byte of the UART RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “ ...
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... NXP Semiconductors Table 92. UART Divisor Latch LSB Register (U0DLL - address 0x4000 8000 when DLAB = 1) bit description Bit Symbol 7:0 DLLSB 31:8 - Table 93. UART Divisor Latch MSB Register (U0DLM - address 0x4000 8004 when DLAB = 1) bit description Bit Symbol 7:0 DLMSB 31:8 - 9.6.4 UART Interrupt Enable Register (U0IER - 0x4000 8004, when DLAB = 0) The U0IER is used to enable the four UART interrupt sources ...
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... NXP Semiconductors 9.6.5 UART Interrupt Identification Register (U0IIR - 0x4004 8008, Read Only) U0IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during a U0IIR access interrupt occurs during a U0IIR access, the interrupt is recorded for the next U0IIR access. ...
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... NXP Semiconductors The UART RDA interrupt (U0IIR[3:1] = 010) shares the second level priority with the CTI interrupt (U0IIR[3:1] = 110). The RDA is activated when the UART Rx FIFO reaches the trigger level defined in U0FCR7:6 and is reset when the UART Rx FIFO depth falls below the trigger level ...
Page 79
... NXP Semiconductors initialization conditions implement a one character delay minus the stop bit whenever THRE = 1 and there have not been at least two characters in the U0THR at one time since the last THRE = 1 event. This delay is provided to give the CPU time to write data to U0THR without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the UART THR FIFO has held two or more characters at one time and currently, the U0THR is empty ...
Page 80
... NXP Semiconductors Table 98. UART Line Control Register (U0LCR - address 0x4000 800C) bit description Bit Symbol Value Description 2 Stop Bit Select 3 Parity Enable 5:4 Parity Select 6 Break Control 7 Divisor Latch Access Bit (DLAB) 31 9.6.8 UART Modem Control Register The U0MCR enables the modem loopback mode and controls the modem output signals. ...
Page 81
... NXP Semiconductors Table 99. UART0 Modem Control Register (U0MCR - address 0x4000 8010) bit description Bit Symbol 4 Loopback Mode Select RTSen 7 CTSen 31:8 - 9.6.8.1 Auto-flow control If auto-RTS mode is enabled the UART‘s receiver FIFO hardware controls the RTS output of the UART. If the auto-CTS mode is enabled the UART‘s U0TSR hardware will only start transmitting if the CTS input signal is asserted ...
Page 82
... NXP Semiconductors Example: Suppose the UART operating in type ‘550 mode has the trigger level in U0FCR set to 0x2, then, if Auto-RTS is enabled, the UART will deassert the RTS output as soon as the receive FIFO contains 8 bytes reasserted as soon as the receive FIFO hits the previous trigger level: 4 bytes. ...
Page 83
... NXP Semiconductors UART1 TX start bits0..7 stop CTS1 pin Fig 10. Auto-CTS Functional Timing While starting transmission of the initial character, the CTS signal is asserted. Transmission will stall as soon as the pending transmission has completed. The UART will continue transmitting a 1 bit as long as CTS is de-asserted (high). As soon as CTS gets de-asserted, transmission resumes and a start bit is sent followed by the data bits of the next character ...
Page 84
... NXP Semiconductors Table 101. UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit description Bit Symbol 3 Framing Error (FE) 4 Break Interrupt (BI) 5 Transmitter Holding Register Empty (THRE) 6 Transmitter Empty (TEMT) 7 Error in RX FIFO (RXFE) 31 9.6.10 UART Modem Status Register The U0MSR is a read-only register that provides status information on the modem input signals ...
Page 85
... NXP Semiconductors Table 102. UART Modem Status Register (U0MSR - address 0x4000 8018) bit description Bit Symbol Value Description 0 Delta CTS 1 Delta DSR 2 Trailing Edge RI 3 Delta DCD 4 CTS 5 DSR DCD 31 9.6.11 UART Scratch Pad Register (U0SCR - 0x4000 801C) The U0SCR has no effect on the UART operation. This register can be written and/or read at user’ ...
Page 86
... NXP Semiconductors Table 104. Auto-baud Control Register (U0ACR - address 0x4000 8020) bit description Bit Symbol 0 Start 1 Mode 2 AutoRestart 0 7 ABEOIntClr 9 ABTOIntClr 31:10 - 9.6.13 Auto-baud The UART auto-baud function can be used to measure the incoming baud rate based on the ”AT" protocol (Hayes command). If enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers U0DLM and U0DLL accordingly ...
Page 87
... NXP Semiconductors The U0ACR AutoRestart bit can be used to automatically restart baud rate measurement if a time-out occurs (the rate measurement counter overflows). If this bit is set, the rate measurement will restart at the next falling edge of the UART Rx pin. The auto-baud function can generate two interrupts. ...
Page 88
... NXP Semiconductors 6. The rate counter is loaded into U0DLM/U0DLL and the baud rate will be switched to normal operation. After setting the U0DLM/U0DLL, the end of auto-baud interrupt U0IIR ABEOInt will be set, if enabled. The U0RSR will now continue receiving the remaining bits of the ”A/a" character. ...
Page 89
... NXP Semiconductors Table 105. UART Fractional Divider Register (U0FDR - address 0x4000 8028) bit description Bit Function 3:0 DIVADDVAL 7:4 MULVAL 31:8 - This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART disabled making sure that UART is fully software and hardware compatible with UARTs not equipped with this feature ...
Page 90
... NXP Semiconductors Pick another FR the range [1.1, 1.9] Fig 12. Algorithm for setting UART dividers UM10415 User manual Chapter 9: EM773 Universal Asynchronous Transmitter (UART) Calculating UART baudrate (BR) PCLK PCLK/(16 x BR) est est integer? False FR = 1.5 est from est DL = Int(PCLK/( est FR = PCLK/( est False 1.1 < ...
Page 91
... NXP Semiconductors Table 106. Fractional Divider setting look-up table FR DivAddVal/ MulVal 1.000 0/1 1.067 1/15 1.071 1/14 1.077 1/13 1.083 1/12 1.091 1/11 1.100 1/10 1.111 1/9 1.125 1/8 1.133 2/15 1.143 1/7 1.154 2/13 1.167 1/6 1.182 2/11 1.200 1/5 1 ...
Page 92
... NXP Semiconductors Although Table 107 control strongly suggested to let UART hardware implemented auto flow control features take care of this, and limit the scope of TxEn to software flow control. Table 107 describes how to use TXEn bit in order to achieve software flow control. Table 107. UART Transmit Enable Register (U0TER - address 0x4000 8030) bit description ...
Page 93
... NXP Semiconductors Table 108. UART RS485 Control register (U0RS485CTRL - address 0x4000 804C) bit description Bit Symbol 31:6 - 9.6.18 UART RS-485 Address Match register (U0RS485ADRMATCH - 0x4000 8050) The U0RS485ADRMATCH register contains the address match value for RS-485/EIA-485 mode. Table 109. UART RS-485 Address Match register (U0RS485ADRMATCH - address ...
Page 94
... NXP Semiconductors RS-485/EIA-485 Normal Multidrop Mode (NMM) Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received data bytes will be ignored and will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘ ...
Page 95
... NXP Semiconductors The driver delay time is the delay between the last stop bit leaving the TXFIFO and the de-assertion of RTS. This delay time can be programmed in the 8-bit RS485DLY register. The delay time is in periods of the baud clock. Any delay time from 0 to 255 bit times may be used ...
Page 96
... NXP Semiconductors U0INTR PA[2:0] PSEL PSTB PWRITE PD[7: PCLK Fig 13. UART block diagram UM10415 User manual Chapter 9: EM773 Universal Asynchronous Transmitter (UART) INTERRUPT U0IER U0IIR U0SCR APB INTERFACE All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 September 2010 UM10415 ...
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UM10415 Chapter 10: EM773 I2C-bus interface Rev. 1 — 10 September 2010 10.1 How to read this chapter 2 The I C-bus block is identical for all EM773 parts. 10.2 Basic configuration 2 The I C-bus interface is configured using ...
Page 98
... C-bus bus 2 Fig 14. I C-bus configuration 2 10.5 Fast-mode Plus Fast-Mode Plus supports a 1 Mbit/sec transfer rate to communicate with the I products which NXP Semiconductors is now providing. UM10415 User manual 2 C specification, supporting the ability to turn pull-up pull-up resistor resistor SCL SDA OTHER DEVICE WITH ...
Page 99
... NXP Semiconductors 10.6 Pin description 2 Table 111. I Pin SDA SCL 2 The I C-bus pins must be configured through the IOCON_PIO0_4 IOCON_PIO0_5 Fast-mode Plus, rates above 400 kHz and MHz may be selected. The I are open-drain outputs and fully compatible with the I 10.7 Clocking and power control ...
Page 100
... NXP Semiconductors 2 Table 112. Register overview (base address 0x4000 0000) Name Access Address offset I2C0ADR1 R/W 0x020 I2C0ADR2 R/W 0x024 I2C0ADR3 R/W 0x028 I2C0DATA_ RO 0x02C BUFFER I2C0MASK0 R/W 0x030 I2C0MASK1 R/W 0x034 I2C0MASK2 R/W 0x038 I2C0MASK3 R/W 0x03C [1] Reset value reflects the data stored in used bits only. It does not include reserved bits content. ...
Page 101
... NXP Semiconductors 2 I2EN I C Interface Enable. When I2EN is 1, the I cleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I interface is disabled. When I2EN is “0”, the SDA and SCL input signals are ignored, the I addressed” slave state, and the STO bit is forced to “0”. ...
Page 102
... NXP Semiconductors 2. The General Call address has been received while the General Call bit (GC) in I2ADR is set data byte has been received while the data byte has been received while the I The AA bit can be cleared by writing 1 to the AAC bit in the I2CONCLR register. When AA ...
Page 103
... NXP Semiconductors Any of these registers which contain the bit 00x will be disabled and will not match any address on the bus. The slave address register will be cleared to this disabled state on reset. See also 2 Table 116. I Bit Symbol Description 0 GC 7:1 Address The I ...
Page 104
... NXP Semiconductors Table 119. I2SCLL + I2SCLH values for selected mode Standard mode Fast-mode Fast-mode Plus I2SCLL and I2SCLH values should not necessarily be the same. Software can set different duty cycles on SCL by setting these two registers. For example, the I specification defines the SCL low time and high time at different values for a Fast-mode ...
Page 105
... NXP Semiconductors 2 Table 121. I Bit Symbol 0 MM_ENA 1 ENA_SCL 2 MATCH_ALL 31:3 - [1] When the ENA_SCL bit is cleared and the I time becomes important. To give the part more time to respond DATA _BUFFER register is used time. Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if the module is NOT in monitor mode) ...
Page 106
... NXP Semiconductors Following all of these interrupts, the processor may read the data register to see what was actually transmitted on the bus. 10.8.7.2 Loss of arbitration in Monitor mode In monitor mode, the I the bus master or issue an ACK). Some other slave on the bus will respond instead. This will most probably result in a lost-arbitration state as far as our module is concerned ...
Page 107
... NXP Semiconductors 2 Table 123. I Bit Symbol 7:0 Data 31 10.8. Mask registers (I2C0MASK[ 0x4000 00[30, 34, 38, 3C]) The four mask registers each contain seven active bits (7:1). Any bit in these registers which is set to ‘1’ will cause an automatic compare on the corresponding bit of the received address when it is compared to the I2ADDRn register associated with that mask register ...
Page 108
... NXP Semiconductors Table 125. I2C0CONSET and I2C1CONSET used to configure Master mode Bit 7 Symbol - Value - The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this mode the data direction bit (R/W) should be 0 which means Write ...
Page 109
... NXP Semiconductors S SLAVE ADDRESS from Master to Slave from Slave to Master Fig 16. Format of Master Receiver mode After a Repeated START condition SLA From master to slave From slave to master Fig 17. A Master Receiver switches to Master Transmitter after sending Repeated START 10.9.3 Slave Receiver mode In the slave receiver mode, data bytes are received from a master transmitter ...
Page 110
... NXP Semiconductors S SLAVE ADDRESS from Master to Slave from Slave to Master Fig 18. Format of Slave Receiver mode 10.9.4 Slave Transmitter mode The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via SDA while the serial clock is input through SCL ...
Page 111
... NXP Semiconductors INPUT FILTER SDA OUTPUT STAGE INPUT FILTER SCL OUTPUT STAGE status STATUS bus DECODER 2 Fig 20 serial interface block diagram 10.10.1 Input filters and output stages Input signals are synchronized with the internal clock, and spikes shorter than three clocks are filtered out. ...
Page 112
... NXP Semiconductors 10.10.2 Address Registers, I2ADDR0 to I2ADDR3 These registers may be loaded with the 7-bit slave address (7 most significant bits which the I C block will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable General Call address (0x00) recognition. When multiple slave addresses are enabled, the actual address received may be read from the I2DAT register at the state where the own slave address has been received ...
Page 113
... NXP Semiconductors SDA line SCL line (1) Another device transmits serial data. (2) Another device overrules a logic (dotted line) transmitted this I low. Arbitration is lost, and this I (3) This I transmitted. This I the new master once it has won arbitration. Fig 21. Arbitration procedure The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device. If two or more master devices generate clock pulses, the “ ...
Page 114
... NXP Semiconductors 2 via the I C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH registers for details. The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above. 10.10.8 Timing and control The timing and control logic generates the timing and control signals for serial byte handling ...
Page 115
... NXP Semiconductors Table 127. Abbreviations used to describe an I Abbreviation S SLA Data P In Figure 23 The numbers in the circles show the status code held in the I2STAT register. At these points, a service routine must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software ...
Page 116
... NXP Semiconductors The master transmitter mode may now be entered by setting the STA bit. The I now test the I When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status code in the status register (I2STAT) will be 0x08. This status code is used by the interrupt service routine to enter the appropriate state service routine that loads I2DAT with the slave address and the data direction bit (SLA+W) ...
Page 117
... NXP Semiconductors Table 129. Master Transmitter mode 2 Status Status of the I C-bus Application software response Code and hardware To/From I2DAT (I2CSTAT) 0x08 A START condition Load SLA+W; has been transmitted. clear STA 0x10 A Repeated START Load SLA+W or condition has been Load SLA+R; transmitted. ...
Page 118
... NXP Semiconductors successful transmission SLA Slave Receiver 08H next transfer started with a Repeated Start condition Not Acknowledge received after the Slave address Not Acknowledge received after a Data byte arbitration lost in Slave address or Data byte arbitration lost and addressed as Slave from Master to Slave ...
Page 119
... NXP Semiconductors 10.11.2 Master Receiver mode In the master receiver mode, a number of data bytes are received from a slave transmitter (see Figure 24). The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the interrupt service routine must load I2DAT with the 7-bit slave address and the data direction bit (SLA+R) ...
Page 120
... NXP Semiconductors Table 130. Master Receiver mode 2 Status Status of the I C-bus Application software response Code and hardware To/From I2DAT (I2CSTAT) 0x08 A START condition Load SLA+R has been transmitted. 0x10 A Repeated START Load SLA+R or condition has been Load SLA+W transmitted. 0x38 Arbitration lost in NOT No I2DAT action ACK bit ...
Page 121
... NXP Semiconductors successful transmission to S SLA a Slave transmitter 08H next transfer started with a Repeated Start condition Not Acknowledge received after the Slave address arbitration lost in Slave address or Acknowledge bit arbitration lost and addressed as Slave from Master to Slave from Slave to Master any number of data bytes and their associated ...
Page 122
... NXP Semiconductors 10.11.3 Slave Receiver mode In the slave receiver mode, a number of data bytes are received from a master transmitter (see Figure 25). To initiate the slave receiver mode, I2ADR and I2CON must be loaded as follows: Table 131. I2C0ADR and I2C1ADR usage in Slave Receiver mode ...
Page 123
... NXP Semiconductors Table 133. Slave Receiver mode 2 Status Status of the I C-bus Application software response Code and hardware To/From I2DAT (I2CSTAT) 0x60 Own SLA+W has No I2DAT action been received; ACK or has been returned. No I2DAT action 0x68 Arbitration lost in No I2DAT action SLA+R/W as master; ...
Page 124
... NXP Semiconductors Table 133. Slave Receiver mode …continued 2 Status Status of the I C-bus Application software response Code and hardware To/From I2DAT (I2CSTAT) 0x98 Previously addressed Read data byte or 0 with General Call; DATA byte has been received; NOT ACK Read data byte or 0 has been returned ...
Page 125
... NXP Semiconductors reception of the own Slave address and one S or more Data bytes all are acknowledged last data byte received is Not acknowledged arbitration lost as Master and addressed as Slave reception of the General Call address and one or more Data bytes last data byte is Not ...
Page 126
... NXP Semiconductors 10.11.4 Slave Transmitter mode In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 26). Data transfer is initialized as in the slave receiver mode. When I2ADR and I2CON have been initialized, the I address followed by the data direction bit which must be “1” (R) for the I operate in the slave transmitter mode ...
Page 127
... NXP Semiconductors Table 134. Slave Transmitter mode 2 Status Status of the I C-bus Application software response Code and hardware To/From I2DAT (I2CSTAT) 0xA8 Own SLA+R has been Load data byte or received; ACK has been returned. Load data byte 0xB0 Arbitration lost in Load data byte or SLA+R/W as master ...
Page 128
... NXP Semiconductors reception of the own Slave address and one or more Data S bytes all are acknowledged arbitration lost as Master and addressed as Slave last data byte transmitted. Switched to Not Addressed Slave (AA bit in I2CON = “0”) from Master to Slave from Slave to Master any number of data bytes and their associated ...
Page 129
... NXP Semiconductors causes the I clear the STO flag (no other bits in I2CON are affected). The SDA and SCL lines are released (a STOP condition is not transmitted). Table 135. Miscellaneous States 2 Status Status of the I C-bus Application software response Code and hardware To/From I2DAT (I2CSTAT) ...
Page 130
... NXP Semiconductors S SLA 08H Fig 27. Simultaneous Repeated START conditions from two masters 10.11.6.2 Data transfer after loss of arbitration Arbitration may be lost in the master transmitter and master receiver modes (see Figure 21). Loss of arbitration is indicated by the following states in I2STAT; 0x38, 0x68, 0x78, and 0xB0 (see ...
Page 131
... NXP Semiconductors 2 10.11.6.4 I C-bus obstructed by a LOW level on SCL or SDA C-bus hang-up can occur if either the SDA or SCL line is held LOW by any device on the bus. If the SCL line is obstructed (pulled LOW device on the bus, no further serial transfer is possible, and the problem must be resolved by the device that is pulling the SCL bus line LOW ...
Page 132
... NXP Semiconductors 10.11.8 Initialization In the initialization example, the I For each mode, a buffer is used for transmission and reception. The initialization routine performs the following functions: • I2ADR is loaded with the part’s own slave address and the General Call bit (GC) • 2 The I C interrupt enable and interrupt priority bits are set • ...
Page 133
... NXP Semiconductors 2. Set up the Slave Address to which data will be transmitted, and add the Write bit. 3. Write 0x20 to I2CONSET to set the STA bit. 4. Set up data to be transmitted in Master Transmit buffer. 5. Initialize the Master data counter to match the length of the message being sent. ...
Page 134
... NXP Semiconductors 5. Set up Master Receive mode data buffer. 6. Initialize Master data counter. 7. Exit 10.12.5.4 State: 0x10 A Repeated START condition has been transmitted. The Slave Address + R/W bit will be transmitted, an ACK bit will be received. 1. Write Slave Address with R/W bit to I2DAT. 2. Write 0x04 to I2CONSET to set the AA bit. ...
Page 135
... NXP Semiconductors 6. Write 0x04 to I2CONSET to set the AA bit. 7. Write 0x08 to I2CONCLR to clear the SI flag. 8. Increment Master Transmit buffer pointer 9. Exit 10.12.6.4 State: 0x30 Data has been transmitted, NOT ACK received. A STOP condition will be transmitted. 1. Write 0x14 to I2CONSET to set the STO and AA bits. ...
Page 136
... NXP Semiconductors 4. Exit 5. Write 0x04 to I2CONSET to set the AA bit. 6. Write 0x08 to I2CONCLR to clear the SI flag. 7. Increment Master Receive buffer pointer 8. Exit 10.12.7.4 State: 0x58 Data has been received, NOT ACK has been returned. Data will be read from I2DAT. A STOP condition will be transmitted. ...
Page 137
... NXP Semiconductors 4. Initialize Slave data counter. 5. Exit 10.12.8.4 State: 0x78 Arbitration has been lost in Slave Address + R/W bit as bus Master. General call has been received and ACK has been returned. Data will be received and ACK returned. STA is set to restart Master mode after the bus is free again. ...
Page 138
... NXP Semiconductors 10.12.8.8 State: 0x98 Previously addressed with General Call. Data has been received, NOT ACK has been returned. Received data will not be saved. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. ...
Page 139
... NXP Semiconductors 2. Write 0x04 to I2CONSET to set the AA bit. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Increment Slave Transmit buffer pointer. 5. Exit 10.12.9.4 State: 0xC0 Data has been transmitted, NOT ACK has been received. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit. ...
Page 140
UM10415 Chapter 11: EM773 SPI0 with SSP Rev. 1 — 10 September 2010 11.1 How to read this chapter The SPI block is identical for all EM773 parts. Remark: The SPI block includes the full SSP feature set, and all ...
Page 141
... NXP Semiconductors 11.5 Pin description Table 136. SPI pin descriptions Pin Type name SCK0 I/O SSEL0 I/O MISO0 I/O MOSI0 I/O Remark: The SCK0 function is multiplexed to two locations on the HVQFN package. Use the IOCON_LOC register (see function in addition to selecting the function in the IOCON registers. ...
Page 142
... NXP Semiconductors 11.6 Clocking and power control The SPI block is gated by the AHBCLKCTRL register (see clock, which is used by the SPI clock divider and prescaler, is controlled by the SSP0CLKDIV registers (see The SPI0_PCLK clocks can be disabled in SSP0CLKDIV registers (see and the SPI blocks can be disabled in the AHBCLKCTRL register savings ...
Page 143
... NXP Semiconductors 11.7.1 SPI/SSP Control Register 0 This register controls the basic operation of the SPI/SSP controller. Table 138: SPI/SSP Control Register 0 (SSP0CR0 - address 0x4004 0000) bit description Bit Symbol Value 3:0 DSS 5:4 FRF 6 CPOL 7 CPHA 15:8 SCR 31:16 - UM10415 User manual Description Data Size Select ...
Page 144
... NXP Semiconductors 11.7.2 SPI/SSP0 Control Register 1 This register controls certain aspects of the operation of the SPI/SSP controller. Table 139: SPI/SSP Control Register 1 (SSP0CR1 - address 0x4004 0004) bit description Bit Symbol 0 LBM 1 SSE SOD 31:4 - UM10415 User manual Value Description Loop Back Mode. ...
Page 145
... NXP Semiconductors 11.7.3 SPI/SSP Data Register Software can write data to be transmitted to this register and read data that has been received. Table 140: SPI/SSP Data Register (SSP0DR - address 0x4004 0008) bit description Bit Symbol 15:0 DATA 31:16 - 11.7.4 SPI/SSP Status Register This read-only register reflects the current status of the SPI controller ...
Page 146
... NXP Semiconductors Table 142: SPI/SSP Clock Prescale Register (SSP0CPSR - address 0x4004 0010) bit description Bit Symbol 7:0 CPSDVSR This even value between 2 and 254, by which SPI_PCLK is 31:8 - Important: the SSPnCPSR value must be properly initialized, or the SPI controller will not be able to transmit data correctly. ...
Page 147
... NXP Semiconductors Table 144: SPI/SSP Raw Interrupt Status register (SSP0RIS - address 0x4004 0018) bit description Bit Symbol 0 RORRIS 1 RTRIS 2 RXRIS 3 TXRIS 31:4 - 11.7.8 SPI/SSP Masked Interrupt Status Register This read-only register contains a 1 for each interrupt condition that is asserted and enabled in the SSPIMSC registers. When an SPI interrupt occurs, the interrupt service routine should read this register to determine the cause(s) of the interrupt ...
Page 148
... NXP Semiconductors Table 146: SPI/SSP interrupt Clear Register (SSP0ICR - address 0x4004 0020) bit description Bit Symbol 0 RORIC 1 RTIC 31:2 - 11.8 Functional description 11.8.1 Texas Instruments synchronous serial frame format Figure 30 shows the 4-wire Texas Instruments synchronous serial frame format supported by the SPI module. ...
Page 149
... NXP Semiconductors Both the SSP and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each CLK. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched. ...
Page 150
... NXP Semiconductors In this configuration, during idle periods: • The CLK signal is forced LOW. • SSEL is forced HIGH. • The transmit MOSI/MISO pad is in high impedance. If the SPI/SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW. This causes slave data to be enabled onto the MISO input line of the master. Master’ ...
Page 151
... NXP Semiconductors If the SPI/SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI pin is enabled. After a further one half SCK period, both master and slave valid data is enabled onto their respective transmission lines ...
Page 152
... NXP Semiconductors If the SPI/SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW, which causes slave data to be immediately transferred onto the MISO line of the master. Master’s MOSI pin is enabled. ...
Page 153
... NXP Semiconductors After all bits have been transferred, in the case of a single word transmission, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured. For continuous back-to-back transmissions, the SSEL pins remains in its active LOW state, until the final bit of the last word has been captured, and then returns to its idle state as described above ...
Page 154
... NXP Semiconductors A transmission is triggered by writing a control byte to the transmit FIFO.The falling edge of CS causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SO pin. CS remains LOW for the duration of the frame transmission ...
Page 155
UM10415 Chapter 12: EM773 16-bit counter/timer (CT16B0) Rev. 1 — 10 September 2010 12.1 How to read this chapter The 16-bit timer block is identical for all EM773 parts. 12.2 Basic configuration The CT16B0 is configured using the following registers: ...
Page 156
... NXP Semiconductors 12.5 Description Each Counter/timer is designed to count cycles of the peripheral clock (PCLK externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt ...
Page 157
... NXP Semiconductors Table 148. Register overview: 16-bit counter/timer 0 CT16B0 (base address 0x4000 C000) Name Access Address offset TMR16B0IR R/W 0x000 TMR16B0TCR R/W 0x004 TMR16B0TC R/W 0x008 TMR16B0PR R/W 0x00C TMR16B0PC R/W 0x010 TMR16B0MCR R/W 0x014 TMR16B0MR0 R/W 0x018 TMR16B0MR1 R/W 0x01C ...
Page 158
... NXP Semiconductors Table 149. Interrupt Register (TMR16B0IR - address 0x4000 C000) bit description Bit Symbol Description 0 MR0 Interrupt Interrupt flag for match channel 0. 1 MR1 Interrupt Interrupt flag for match channel 1. 2 MR2 Interrupt Interrupt flag for match channel 2. 3 MR3 Interrupt Interrupt flag for match channel 3 ...
Page 159
... NXP Semiconductors Table 151. Match Control Register (TMR16B0MCR - address 0x4000 C014) bit description Bit Symbol Value Description 0 MR0I 1 Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 This interrupt is disabled 1 MR0R 1 Reset on MR0: the TC will be reset if MR0 matches it. ...
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... NXP Semiconductors 12.8.8 Capture Control Register (TMR16B0CCR) The Capture Control Register is used to control whether the Capture Register is loaded with the value in the Counter/timer when the capture event occurs, and whether an interrupt is generated by the capture event. Setting both the rising and falling bits at the same time is a valid configuration, resulting in a capture event for both edges. In the description below, " ...
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... NXP Semiconductors Table 153. External Match Register (TMR16B0EMR - address 0x4000 C03C) bit description Bit Symbol Description 0 EM0 External Match 0. This bit reflects the state of output CT16B0_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH nothing ...
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... NXP Semiconductors rising edge, falling edge, either of edges or no changes in the level of the selected CAP input. Only if the identified event occurs, and the event corresponds to the one selected by bits 1:0 in the CTCR register, will the Timer Counter register be incremented. Effective processing of the externally supplied clock to the counter has some limitations. ...
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... NXP Semiconductors Table 156. PWM Control Register (TMR16B0PWMC - address 0x4000 C074 and TMR16B1PWMC- address 0x4001 0074) bit description Bit Symbol 0 PWM enable 1 PWM enable 2 PWM enable 3 PWM enable 31:4 - 12.8.13 Rules for single edge controlled PWM outputs 1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle (timer is set to zero) unless their match value is equal to zero ...
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... NXP Semiconductors Fig 38. Sample PWM waveforms with a PWM cycle length of 100 (selected by MR3) and MAT3:0 enabled as PWM outputs by the PWCON register. 12.9 Example timer operation Figure 39 shows a timer configured to reset the count and generate an interrupt on match. The prescaler is set to 2 and the match register set the end of the timer cycle where the match occurs, the timer count is reset ...
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... NXP Semiconductors 12.10 Architecture The block diagram for counter/timer0 and counter/timer1 is shown in Fig 41. 16-bit counter/timer block diagram UM10415 User manual Chapter 12: EM773 16-bit counter/timer (CT16B0) MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER INTERRUPT REGISTER ...
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UM10415 Chapter 13: EM773 32-bit counter/timers (CT32B0/1) Rev. 1 — 10 September 2010 13.1 How to read this chapter The 32-bit timer blocks are identical for all EM773 parts. 13.2 Basic configuration The CT32B0/1 are configured using the following registers: ...
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... NXP Semiconductors 13.5 Description Each Counter/timer is designed to count cycles of the peripheral clock (PCLK externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt ...
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... NXP Semiconductors Table 158. Register overview: 32-bit counter/timer 0 CT32B0 (base address 0x4001 4000) Name Access Address offset TMR32B0IR R/W 0x000 TMR32B0TCR R/W 0x004 TMR32B0TC R/W 0x008 TMR32B0PR R/W 0x00C TMR32B0PC R/W 0x010 TMR32B0MCR R/W 0x014 TMR32B0MR0 R/W 0x018 TMR32B0MR1 R/W 0x01C ...
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... NXP Semiconductors Table 159. Register overview: 32-bit counter/timer 1 CT32B1 (base address 0x4001 8000) Name Access Address offset TMR32B1IR R/W 0x000 TMR32B1TCR R/W 0x004 TMR32B1TC R/W 0x008 TMR32B1PR R/W 0x00C TMR32B1PC R/W 0x010 TMR32B1MCR R/W 0x014 TMR32B1MR0 R/W 0x018 TMR32B1MR1 R/W 0x01C ...
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... NXP Semiconductors Table 160: Interrupt Register (TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000) bit description Bit Symbol Description 3 MR3 Interrupt Interrupt flag for match channel 3. 4 CR0 Interrupt Interrupt flag for capture channel 0 event. 31:5 - Reserved 13.8.2 Timer Control Register (TMR32B0TCR and TMR32B1TCR) The Timer Control Register (TCR) is used to control the operation of the counter/timer ...
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... NXP Semiconductors 13.8.6 Match Control Register (TMR32B0MCR and TMR32B1MCR) The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter. The function of each of the bits is shown in Table 162. Table 162: Match Control Register (TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014) ...
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... NXP Semiconductors 13.8.7 Match Registers (TMR32B0MR0/1/2/3 - addresses 0x4001 4018/1C/20/24 and TMR32B1MR0/1/2/3 addresses 0x4001 8018/1C/20/24) The Match register values are continuously compared to the Timer Counter value. When the two values are equal, actions can be triggered automatically. The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register ...
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... NXP Semiconductors Table 164: External Match Register (TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C) bit description Bit Symbol Description 0 EM0 External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH nothing ...
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... NXP Semiconductors When Counter Mode is chosen as a mode of operation, the CAP input (selected by the CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two consecutive samples of this CAP input, one of the following four events is recognized: rising edge, falling edge, either of edges or no changes in the level of the selected CAP input ...
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... NXP Semiconductors HIGH. The timer is reset by the match register that is configured to set the PWM cycle length. When the timer is reset to zero, all currently HIGH match outputs configured as PWM outputs are cleared. Table 167: PWM Control Register (TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC - ...
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... NXP Semiconductors Fig 42. Sample PWM waveforms with a PWM cycle length of 100 (selected by MR3) and MAT3:0 enabled as PWM outputs by the PWCON register. 13.9 Example timer operation Figure 43 shows a timer configured to reset the count and generate an interrupt on match. The prescaler is set to 2 and the match register set the end of the timer cycle where the match occurs, the timer count is reset ...
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... NXP Semiconductors 13.10 Architecture The block diagram for 32-bit counter/timer0 and 32-bit counter/timer1 is shown in Figure 45. Fig 45. 32-bit counter/timer block diagram UM10415 User manual Chapter 13: EM773 32-bit counter/timers (CT32B0/1) MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER ...
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UM10415 Chapter 14: EM773 WatchDog Timer (WDT) Rev. 1 — 10 September 2010 14.1 How to read this chapter The WDT block is identical for all EM773 parts. 14.2 Basic configuration The WDT is configured using the following registers: 1. ...
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... NXP Semiconductors 14.5 Description The Watchdog consists of a divide by 4 fixed pre-scaler and a 24-bit counter. The clock is fed to the timer via a pre-scaler. The timer decrements when clocked. The minimum value from which the counter decrements is 0xFF. Setting a value lower than 0xFF causes 0xFF to be loaded in the counter ...
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... NXP Semiconductors Table 168. Register overview: Watchdog timer (base address 0x4000 4000) Name WDMOD WDTC WDFEED WDTV [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. 14.7.1 Watchdog Mode register (WDMOD - 0x4000 0000) The WDMOD register controls the operation of the Watchdog through the combination of WDEN and RESET bits ...
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... NXP Semiconductors Table 170. Watchdog operating modes selection WDEN 14.7.2 Watchdog Timer Constant register (WDTC - 0x4000 4004) The WDTC register determines the time-out value. Every time a feed sequence occurs the WDTC content is reloaded in to the Watchdog timer. It’s a 32-bit register with 8 LSB set reset ...
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... NXP Semiconductors When reading the value of the 24-bit timer, the lock and synchronization procedure takes WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual value of the timer when it's being read by the CPU. Table 173. Watchdog Timer Value register (WDTV - address 0x4000 000C) bit description ...
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UM10415 Chapter 15: EM773 System tick timer Rev. 1 — 10 September 2010 15.1 How to read this chapter The system tick timer (SysTick timer) is part of the ARM Cortex-M0 core and is identical for all EM773 parts. 15.2 ...
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... NXP Semiconductors 15.5 Operation The SysTick timer is a 24-bit timer that counts down to zero and generates an interrupt. The intent is to provide a fixed 10 millisecond time interval between interrupts. The SysTick timer is clocked from the CPU clock. In order to generate recurring interrupts at a specific interval, the SYST_RVR register must be initialized with the correct value for the desired interval. A default value (< ...
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... NXP Semiconductors 15.6.1 System Timer Control and status register The SYST_CSR register contains control information for the SysTick timer and provides a status flag. This register is part of the ARM Cortex-M0 core system timer register block. For a bit description of this register, see 15.6.2 System Timer Reload value register The SYST_RVR register is set to the value that will be loaded into the SysTick timer whenever it counts down to zero ...
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... NXP Semiconductors 15.7 Example timer calculations To use the system tick timer, do the following: 1. Program the SYST_RVR register with the reload value RELOAD to obtain the desired time interval. 2. Clear the SYST_CVR register by writing to it. This ensures that the timer will count from the SYST_RVR value rather than an arbitrary value when the timer is enabled. ...
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UM10415 Chapter 16: EM773 Metrology engine Rev. 1 — 10 September 2010 16.1 How to read this chapter The EM773 Metrology Engine is available on part EM773 only. 16.2 Introduction The Metrology Engine performs electricity measurements for one second periods. ...
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... NXP Semiconductors 16.3 Features • Metrology Engine for Energy Measurements • Outputs RMS voltage (V), RMS current (I), active power (P), apparent power (S), non-active power (N), power factor (PF), fundamental reactive power (Q1), fundamental apparent power (S1), fundamental power factor (PF1), non-fundamental apparent power (SN) and current total harmonic distortion (THDI) according to IEEE Std 1459-2010 • ...
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... NXP Semiconductors The analog front end external to the EM773 must maintain the voltage at the I_LOWGAIN pin between V signals. For maximum dynamic range this bias should be 0 operation, the gain of the analog front end for the I_LOWGAIN channel external to the EM773 should approximately be 1/16 times the gain for the I_HIGHGAIN channel. ...
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... NXP Semiconductors Apparent Power: S — The apparent power S in Volt-Ampere (VA) is measured as the product of the RMS voltage and RMS current: Active Power: P — The active power P in Watt (W) is measured according to: Non-active Power: N — The non-active power N in Volt-Ampere-reactive (var) is measured according to: Power Factor: PF — ...
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... NXP Semiconductors Fundamental Apparent Power: S1 — The fundamental apparent power S1 in Volt-Ampere (VA) is measured according to: Fundamental Power Factor: PF1 — The dimensionless parameter fundamental power factor PF1 is measured as the ratio between fundamental active power P1 and fundamental apparent power S1: Nonfundamental Apparent Power: SN — The nonfundamental apparent power SN in Volt-Ampere (VA) is measured according to: Current Total Harmonic Distortion: THDI — ...
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... NXP Semiconductors 16.6 Operation This section explains the configuration data and calibration procedure for the Metrology Engine. Details on the Metrology Engine interface are described in 16.6.1 Configuration data Summarizes the Metrology Engine configuration parameters. Table 179. Metrology Engine configuration parameters Member Vpp ...
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... NXP Semiconductors 16.6.1.3 Current measurement input range I2pp The parameter I2pp for the I_LOWGAIN input depends on the transfer of the analog input circuit in front of the Metrology Engine and it sets the peak-to-peak range for the second current channel (in Ampere). The input circuit for this channel should be designed in such a way that this range is approximately 16 * I1pp for an optimized accuracy curve ...
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... NXP Semiconductors 16.6.2 Calibration procedure The Metrology Engine can be calibrated by changing the configuration parameters for an individual meter. Before calibration, make sure to set the right values for AHBClkFrequency and mains frequency Fmains with the initialization of the Metrology Engine. The Calibration Measurements Setup is shown in ...
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... NXP Semiconductors • Set this new value as Vpp The calibration can be verified by checking the measured voltage V again. This should now equal Vsource. 16.6.2.2 I1pp calibration The current input measurement range I1pp can be calibrated as follows: • Calculate the initial value for I1pp with the transfer of the analog input circuit in front of ...
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... NXP Semiconductors The calibration can be verified by checking the measured current I again. This should now equal Iref2. 16.6.2.4 DeltaPhi1 calibration The phase error correction angle DeltaPhi1 can be calibrated as follows: • Connect an AC reference voltage source to the meter with the correct voltage and frequency (e.g. 110V/60Hz or 230V/50Hz). • ...
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UM10415 Chapter 17: EM773 Metrology engine interface Rev. 1 — 10 September 2010 17.1 How to read this chapter The EM773 Metrology Engine is available on part EM773 only. 17.2 Metrology driver interface The following seven interfaces of the metrology ...
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... NXP Semiconductors 17.2.4 Metrology Engine start This interface must be called by the application software after the metrology engine is initialized and the ranges are set. This interface enables the measurements by the metrology engine. 17.2.5 Metrology Engine stop This interface must be called by the application software after the metrology engine is initialized, the ranges are set and the engine is started ...
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... NXP Semiconductors metrology_set_ranges(&metrology_ranges); 3. Start the metrology engine: metrology_start(); 4. Read the measured data: while (running (metrology_get_gainchannel() == CURRENT_CHANNEL1) { LED_ON(); /* signal measuring from I_HIGHGAIN */ } else { LED_OFF();/* signal measuring from I_LOWGAIN */ } if (metrology_read_data(&meter_result)) { print_result(&meter_result); } ms_sleep(250 Stop the metrology engine: metrology_stop(); 17.4 Metrology driver structure definitions 17 ...
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... NXP Semiconductors { float V; float I; float P; float Q1; float S; float S1; float PF; float PF1; float SN; float N; float THDI; } metrology_result_t; The members of the metrology result class structure are explained in Table 180. Metrology result class structure Member PF1 SN N THDI UM10415 User manual Chapter 17: EM773 Metrology engine interface ...