OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 281

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
20.5.2.7.1 Hardware and software control of interrupts
20.5.2.7 Level-sensitive and pulse interrupts
See
array, which provides the software view of the interrupt priorities.
Find the IPR number and byte offset for interrupt M as follows:
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also
described as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt
signal. Typically this happens because the ISR accesses the peripheral, causing it to clear
the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the
rising edge of the processor clock. To ensure the NVIC detects the interrupt, the
peripheral must assert the interrupt signal for at least one clock cycle, during which the
NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the
interrupt, see
deasserted before the processor returns from the ISR, the interrupt becomes pending
again, and the processor must execute its ISR again. This means that the peripheral can
hold the interrupt signal asserted until it no longer needs servicing.
The Cortex-M0 latches all interrupts. A peripheral interrupt becomes pending for one of
the following reasons:
A pending interrupt remains pending until one of the following:
•
•
•
•
•
•
the corresponding IPR number, N, is given by N = N DIV 4
the byte offset of the required Priority field in this register is M MOD 4, where:
– byte offset 0 refers to register bits[7:0]
– byte offset 1 refers to register bits[15:8]
– byte offset 2 refers to register bits[23:16]
– byte offset 3 refers to register bits[31:24].
the NVIC detects that the interrupt signal is active and the corresponding interrupt is
not active
the NVIC detects a rising edge on the interrupt signal
software writes to the corresponding interrupt set-pending register bit, see
Section
The processor enters the ISR for the interrupt. This changes the state of the interrupt
from pending to active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC
Section 20–20.5.2.1
samples the interrupt signal. If the signal is asserted, the state of the interrupt
changes to pending, which might cause the processor to immediately re-enter the
ISR. Otherwise, the state of the interrupt changes to inactive.
20–20.5.2.4.
Section
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
20.5.2.7.1. For a level-sensitive interrupt, if the signal is not
for more information about the access to the interrupt priority
Chapter 20: Appendix EM773 ARM Cortex-M0 reference
UM10415
© NXP B.V. 2010. All rights reserved.
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