OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 10

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
3.4 Register description
Table 3.
UM10415
User manual
Name
SYSMEMREMAP
PRESETCTRL
SYSPLLCTRL
SYSPLLSTAT
-
SYSOSCCTRL
WDTOSCCTRL
IRCCTRL
-
Fig 3.
watchdog oscillator
system oscillator
IRC oscillator
IRC oscillator
EM773 CGU block diagram
(system PLL clock select)
Register overview: system control block (base address 0x4004 8000)
SYSPLLCLKSEL
Access
R/W
R/W
R/W
R
-
R/W
R/W
R/W
-
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
See
the system setup. This register is not part of the system configuration block.
Section 3.10
SYSTEM PLL
(main clock select)
Address offset Description
0x000
0x004
0x008
0x00C
0x010 - 0x01C
0x020
0x024
0x028
0x02C
MAINCLKSEL
All information provided in this document is subject to legal disclaimers.
main clock
for the flash access timing register, which can be re-configured as part
Rev. 1 — 10 September 2010
System memory remap
Peripheral reset control
System PLL control
System PLL status
Reserved
System oscillator control
Watchdog oscillator control
IRC control
Reserved
watchdog oscillator
watchdog oscillator
system oscillator
SYSTEM CLOCK
IRC oscillator
IRC oscillator
DIVIDER
(WDT clock update enable)
(CLKOUT update enable)
CLKOUTUEN
WDTUEN
system clock
Chapter 3: EM773 System configuration
AHBCLKCTRL[1:18]
(AHB clock enable)
CLKOUT PIN CLOCK
UART PERIPHERAL
SPI0 PERIPHERAL
CLOCK DIVIDER
CLOCK DIVIDER
18
WDT CLOCK
DIVIDER
DIVIDER
Reset
value
0x002
0x000
0x000
0x000
-
0x000
0x000
0x080
-
UM10415
AHB clocks 1 to 18
(memories
and peripherals)
AHB clock 0
(system)
© NXP B.V. 2010. All rights reserved.
em773_002aae514
SPI0
UART
WDT
CLKOUT pin
Reference
Table 4
Table 5
Table 6
Table 7
-
Table 8
Table 9
Table 10
-
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