OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 69

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
8.4 Functional description
UM10415
User manual
8.3.8 GPIO masked interrupt status register
8.3.9 GPIO interrupt clear register
8.4.1 Write/read data operation
Bits read HIGH in the GPIOnMIS register reflect the status of the input lines triggering an
interrupt. Bits read as LOW indicate that either no interrupt on the corresponding input
pins has been generated or that the interrupt is masked. GPIOMIS is the state of the
interrupt after masking. The register is read-only.
Table 86.
This register allows software to clear edge detection for port bits that are identified as
edge-sensitive in the Interrupt Sense register. This register has no effect on port bits
identified as level-sensitive.
Table 87.
In order for software to be able to set GPIO bits without affecting any other pins in a single
write operation, bits [13:2] of a 14-bit wide address bus are used to create a 12-bit wide
mask for write and read operations on the 12 GPIO pins for each port. Only GPIOnDATA
bits masked by 1 are affected by read and write operations. The masked GPIOnDATA
register can be located anywhere between address offsets 0x0000 to 0x3FFC in the
GPIOn address space. Reading and writing to the GPIOnDATA register at address
0x3FFC sets all masking bits to 1.
Write operation
Bit
11:0
31:12
Bit
11:0
31:12
Symbol Value Description
MASK
-
Symbol
CLR
-
GPIOnMIS register (GPIO0MIS, address 0x5000 8018 to GPIO3MIS, address
0x5003 8018) bit description
GPIOnIC register (GPIO0IC, address 0x5000 801C to GPIO3IC, address 0x5003
801C) bit description
All information provided in this document is subject to legal disclaimers.
0
1
-
Value
0
1
-
Rev. 1 — 10 September 2010
Selects interrupt on pin x to be masked (x = 0 to 11).
No interrupt or interrupt masked on pin PIOn_x.
Interrupt on PIOn_x.
Reserved
Description
Selects interrupt on pin x to be cleared (x = 0 to
11). Clears the interrupt edge detection logic. This
register is write-only.
Remark: The synchronizer between the GPIO and
the NVIC blocks causes a delay of 2 clocks. It is
recommended to add two NOPs after the clear of
the interrupt edge detection logic before the exit of
the interrupt service routine.
No effect.
Clears edge detection logic for pin PIOn_x.
Reserved
Chapter 8: EM773 General Purpose I/O (GPIO)
UM10415
© NXP B.V. 2010. All rights reserved.
Reset
value
0x00
-
0x00
-
Reset
value
Access
W
-
Access
R
-
69 of 310