OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 143

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
11.7.1 SPI/SSP Control Register 0
This register controls the basic operation of the SPI/SSP controller.
Table 138: SPI/SSP Control Register 0 (SSP0CR0 - address 0x4004 0000) bit description
Bit
3:0
5:4
6
7
15:8
31:16 -
Symbol Value
DSS
FRF
CPOL
CPHA
SCR
All information provided in this document is subject to legal disclaimers.
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
00
01
10
11
0
1
0
1
-
Rev. 1 — 10 September 2010
Description
Data Size Select. This field controls the number of bits
transferred in each frame. Values 0000-0010 are not
supported and should not be used.
4-bit transfer
5-bit transfer
6-bit transfer
7-bit transfer
8-bit transfer
9-bit transfer
10-bit transfer
11-bit transfer
12-bit transfer
13-bit transfer
14-bit transfer
15-bit transfer
16-bit transfer
Frame Format.
SPI
TI
Microwire
This combination is not supported and should not be used.
Clock Out Polarity. This bit is only used in SPI mode.
SPI controller maintains the bus clock low between frames.
SPI controller maintains the bus clock high between frames.
Clock Out Phase. This bit is only used in SPI mode.
SPI controller captures serial data on the first clock transition
of the frame, that is, the transition away from the inter-frame
state of the clock line.
SPI controller captures serial data on the second clock
transition of the frame, that is, the transition back to the
inter-frame state of the clock line.
Serial Clock Rate. The number of prescaler-output clocks per
bit on the bus, minus one. Given that CPSDVSR is the
prescale divider, and the APB clock PCLK clocks the
prescaler, the bit frequency is PCLK / (CPSDVSR × [SCR+1]).
Reserved
Chapter 11: EM773 SPI0 with SSP
UM10415
© NXP B.V. 2010. All rights reserved.
143 of 310
Reset
Value
0000
00
0
0
0x00
-