OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 146

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
11.7.6 SPI/SSP Interrupt Mask Set/Clear Register
11.7.7 SPI/SSP Raw Interrupt Status Register
Table 142: SPI/SSP Clock Prescale Register (SSP0CPSR - address 0x4004 0010) bit
Important: the SSPnCPSR value must be properly initialized, or the SPI controller will not
be able to transmit data correctly.
In Slave mode, the SPI clock rate provided by the master must not exceed 1/12 of the SPI
peripheral clock selected in
relevant.
In master mode, CPSDVSR
This register controls whether each of the four possible interrupt conditions in the SPI
controller are enabled. Note that ARM uses the word “masked” in the opposite sense from
classic computer terminology, in which “masked” meant “disabled”. ARM uses the word
“masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.
Table 143: SPI/SSP Interrupt Mask Set/Clear register (SSP0IMSC - address 0x4004 0014) bit
This read-only register contains a 1 for each interrupt condition that is asserted,
regardless of whether or not the interrupt is enabled in the SSPIMSC registers.
Bit
7:0
31:8
Bit
0
1
2
3
31:4
Symbol
CPSDVSR This even value between 2 and 254, by which SPI_PCLK is
-
Symbol
RORIM
RTIM
RXIM
TXIM
-
description
description
All information provided in this document is subject to legal disclaimers.
Description
divided to yield the prescaler output clock. Bit 0 always reads
as 0.
Reserved.
Description
Software should set this bit to enable interrupt when a Receive
Overrun occurs, that is, when the Rx FIFO is full and another frame is
completely received. The ARM spec implies that the preceding frame
data is overwritten by the new frame data when this occurs.
Software should set this bit to enable interrupt when a Receive
Timeout condition occurs. A Receive Timeout occurs when the Rx
FIFO is not empty, and no has not been read for a "timeout period".
The timeout period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR ×
[SCR+1]).
Software should set this bit to enable interrupt when the Rx FIFO is at
least half full.
Software should set this bit to enable interrupt when the Tx FIFO is at
least half empty.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 1 — 10 September 2010
Section
min
= 2 or larger (even numbers only).
3.4.15. The content of the SSPnCPSR register is not
Chapter 11: EM773 SPI0 with SSP
UM10415
© NXP B.V. 2010. All rights reserved.
Reset Value
0
-
146 of 310
Reset
Value
0
0
0
0
NA