OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 83

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
Fig 10. Auto-CTS Functional Timing
UART1 TX
CTS1 pin
9.6.9 UART Line Status Register (U0LSR - 0x4000 8014, Read Only)
start
bits0..7
While starting transmission of the initial character, the CTS signal is asserted.
Transmission will stall as soon as the pending transmission has completed. The UART will
continue transmitting a 1 bit as long as CTS is de-asserted (high). As soon as CTS gets
de-asserted, transmission resumes and a start bit is sent followed by the data bits of the
next character.
The U0LSR is a Read Only register that provides status information on the UART TX and
RX blocks.
Table 101. UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit
Bit Symbol
0
1
2
Receiver
Data Ready
(RDR)
Overrun
Error
Parity Error
(OE)
(PE)
stop
description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
Rev. 1 — 10 September 2010
Chapter 9: EM773 Universal Asynchronous Transmitter (UART)
Receiver Data Ready:U0LSR[0] is set when the U0RBR holds
an unread character and is cleared when the UART RBR FIFO
is empty.
U0RBR is empty.
U0RBR contains valid data.
The overrun error condition is set as soon as it occurs. A
U0LSR read clears U0LSR[1]. U0LSR[1] is set when UART
RSR has a new character assembled and the UART RBR FIFO
is full. In this case, the UART RBR FIFO will not be overwritten
and the character in the UART RSR will be lost.
Overrun error status is inactive.
Overrun error status is active.
When the parity bit of a received character is in the wrong state,
a parity error occurs. A U0LSR read clears U0LSR[2]. Time of
parity error detection is dependent on U0FCR[0].
Note: A parity error is associated with the character at the top of
the UART RBR FIFO.
Parity error status is inactive.
Parity error status is active.
start
bits0..7
stop
start
UM10415
© NXP B.V. 2010. All rights reserved.
bits0..7
83 of 310
stop
Reset
Value
0
0
0