OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 296

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
21.4 Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Internal resonant crystal control register
Table 11. System reset status register (SYSRSTSTAT,
Table 12. System PLL clock source select register
Table 13. System PLL clock source update enable register
Table 14. Main clock source select register (MAINCLKSEL,
Table 15. Main clock source update enable register
Table 16. System AHB clock divider register
Table 17. System AHB clock control register
Table 18. SPI0 clock divider register (SSP0CLKDIV,
Table 19. UART clock divider register (UARTCLKDIV,
Table 20. WDT clock source select register (WDTCLKSEL,
Table 21. WDT clock source update enable register
Table 22. WDT clock divider register (WDTCLKDIV, address
Table 23. CLKOUT clock source select register
Table 24. CLKOUT clock source update enable register
UM10415
User manual
Ordering information . . . . . . . . . . . . . . . . . . . . .4
Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Register overview: system control block (base
address 0x4004 8000) . . . . . . . . . . . . . . . . . .10
System memory remap register
(SYSMEMREMAP, address 0x4004 8000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Peripheral reset control register (PRESETCTRL,
address 0x4004 8004) bit description. . . . . . . .12
System PLL control register (SYSPLLCTRL,
address 0x4004 8008) bit description . . . . . . .13
System PLL status register (SYSPLLSTAT,
address 0x4004 800C) bit description . . . . . . .13
System oscillator control register (SYSOSCCTRL,
address 0x4004 8020) bit description. . . . . . . .13
Watchdog oscillator control register
(WDTOSCCTRL, address 0x4004 8024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
(IRCCTRL, address 0x4004 8028) bit description
15
address 0x4004 8030) bit description. . . . . . . .16
(SYSPLLCLKSEL, address 0x4004 8040) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
(SYSPLLUEN, address 0x4004 8044) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
address 0x4004 8070) bit description. . . . . . . .17
(MAINCLKUEN, address 0x4004 8074) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
(SYSAHBCLKDIV, address 0x4004 8078) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
(SYSAHBCLKCTRL, address 0x4004 8080) bit
description
address 0x4004 8094) bit description. . . . . . . .20
address 0x4004 8098) bit description. . . . . . . .20
address 0x4004 80D0) bit description . . . . . . .21
(WDTCLKUEN, address 0x4004 80D4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
0x4004 80D8) bit description . . . . . . . . . . . . . .21
(CLKOUTCLKSEL, address 0x4004 80E0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
(CLKOUTUEN, address 0x4004 80E4) bit
. . . . . . . . . . . . . . . . . . . . . . . . . . .18
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
Table 25. CLKOUT clock divider registers
Table 26. POR captured PIO status registers 0
Table 27. POR captured PIO status registers 1
Table 28. BOD control register (BODCTRL, address 0x4004
Table 29. System tick timer calibration register
Table 30. Start logic edge control register 0 (STARTAPRP0,
Table 31. Start logic signal enable register 0 (STARTERP0,
Table 32. Start logic reset register 0 (STARTRSRP0CLR,
Table 33. Start logic status register 0 (STARTSRP0,
Table 34. Allowed values for PDSLEEPCFG register . . . 26
Table 35. Deep-sleep configuration register
Table 36. Wake-up configuration register (PDAWAKECFG,
Table 37. Power-down configuration register (PDRUNCFG,
Table 38. Device ID register (DEVICE_ID, address 0x4004
Table 39. PLL frequency parameters. . . . . . . . . . . . . . . . 37
Table 40. PLL configuration examples. . . . . . . . . . . . . . . 37
Table 41. Flash configuration register (FLASHCFG, address
Table 42. Register overview: PMU (base address 0x4003
Table 43. Power control register (PCON, address 0x4003
Table 44. General purpose registers 0 to 3 (GPREG0 -
Table 45. General purpose register 4 (GPREG4, address
Table 46. Connection of interrupt sources to the Vectored
Table 47. Register overview: I/O configuration (base
Table 48. I/O configuration registers ordered by port number
Table 49. IOCON_PIO2_0 register (IOCON_PIO2_0,
Table 50. IOCON_nRESET_PIO0_0 register
Chapter 21: EM773 Supplementary information
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
(CLKOUTCLKDIV, address 0x4004 80E8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
(PIOPORCAP0, address 0x4004 8100) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
(PIOPORCAP1, address 0x4004 8104) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8150) bit description. . . . . . . . . . . . . . . . . . . . . 23
(SYSTCKCAL, address 0x4004 8158) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
address 0x4004 8200) bit description . . . . . . 24
address 0x4004 8204) bit description . . . . . . 25
address 0x4004 8208) bit description . . . . . . 25
address 0x4004 820C) bit description . . . . . . 25
(PDSLEEPCFG, address 0x4004 8230) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
address 0x4004 8234) bit description . . . . . . 27
address 0x4004 8238) bit description . . . . . . 28
83F4) bit description . . . . . . . . . . . . . . . . . . . . 29
0x4003 C010) bit description . . . . . . . . . . . . . . 38
8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8000) bit description . . . . . . . . . . . . . . . . . . . . 39
GPREG3, address 0x4003 8004 to 0x4003 8010)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 40
0x4003 8014) bit description . . . . . . . . . . . . . 40
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . 41
address 0x4004 4000) . . . . . . . . . . . . . . . . . . . 45
46
address 0x4004 4008) bit description . . . . . . . 47
(IOCON_nRESET_PIO0_0, address 0x4004
UM10415
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