OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 150

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
11.8.2.3 SPI format with CPOL=0,CPHA=1
In this configuration, during idle periods:
If the SPI/SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW. This causes slave
data to be enabled onto the MISO input line of the master. Master’s MOSI is enabled.
One half SCK period later, valid master data is transferred to the MOSI pin. Now that both
the master and slave data have been set, the SCK master clock pin goes HIGH after one
further half SCK period.
The data is captured on the rising and propagated on the falling edges of the SCK signal.
In the case of a single word transmission, after all bits of the data word have been
transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last
bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSEL signal must be
pulsed HIGH between each data word transfer. This is because the slave select pin
freezes the data in its serial peripheral register and does not allow it to be altered if the
CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave
device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK
period after the last bit has been captured.
The transfer signal sequence for SPI format with CPOL = 0, CPHA = 1 is shown in
Figure
In this configuration, during idle periods:
Fig 32. SPI frame format with CPOL=0 and CPHA=1
•
•
•
•
•
•
The CLK signal is forced LOW.
SSEL is forced HIGH.
The transmit MOSI/MISO pad is in high impedance.
The CLK signal is forced LOW.
SSEL is forced HIGH.
The transmit MOSI/MISO pad is in high impedance.
32, which covers both single and continuous transfers.
All information provided in this document is subject to legal disclaimers.
SSEL
MOSI
MISO
SCK
Rev. 1 — 10 September 2010
Q
MSB
MSB
4 to 16 bits
Chapter 11: EM773 SPI0 with SSP
LSB
LSB
Q
UM10415
© NXP B.V. 2010. All rights reserved.
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