OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 20

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
3.4.15 SPI0 clock divider register
3.4.16 UART clock divider register
3.4.17 WDT clock source select register
Table 17.
This register configures the SPI0 peripheral clock SPI0_PCLK. The SPI0_PCLK can be
shut down by setting the DIV bits to 0x0.
Table 18.
This register configures the UART peripheral clock UART_PCLK. The UART_PCLK can
be shut down by setting the DIV bits to 0x0.
Remark: Note that the UART pins must be configured in the IOCON block before the
UART clock can be enabled.
Table 19.
This register selects the clock source for the watchdog timer. The WDTCLKUEN register
(see
Bit
16
17
18
31:19
Bit
7:0
31:8
Bit
7:0
31:8
Section
Symbol
IOCON
-
-
-
Symbol
DIV
-
Symbol
DIV
-
System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
SPI0 clock divider register (SSP0CLKDIV, address 0x4004 8094) bit description
UART clock divider register (UARTCLKDIV, address 0x4004 8098) bit description
3.4.18) must be toggled from LOW to HIGH for the update to take effect.
All information provided in this document is subject to legal disclaimers.
Value
0
1
to
255
-
Value
0
1
to
255
-
Rev. 1 — 10 September 2010
…continued
Value
0
1
-
-
-
Description
SPI0_PCLK clock divider values
Disable SPI0_PCLK.
Divide by 1.
...
Divide by 255.
Reserved
Description
UART_PCLK clock divider values
Disable UART_PCLK.
Divide by 1.
...
Divide by 255.
Reserved
Description
Enables clock for I/O configuration block.
Disable
Enable
Reserved
Reserved
Reserved
Chapter 3: EM773 System configuration
UM10415
© NXP B.V. 2010. All rights reserved.
Reset
value
0
0
0
0x00
Reset
value
0x00
0x00
Reset
value
0x00
0x00
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