MT46V16M16P-5B:K Micron Technology Inc, MT46V16M16P-5B:K Datasheet - Page 17

• Manufacturer Part Number: MT46V16M16P-5B:K
• Description: DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.6V 66-Pin TSOP Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V16M16P-5B:K

• Density: 256 Mb
• Maximum Clock Rate: 400 MHz
• Package: 66TSOP
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 2.6 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: 0 to 70 °C
• Organization: 16Mx16
• Address Bus: 15b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.6V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Supply Current: 260mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Electrical Specifications – I
Table 6:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
256Mb_DDR_x4x8x16_D2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Parameter/Condition
Operating one-bank precharge current:
t
clock cycle; Address and control inputs changing once every
two clock cycles
Operating one-bank active-read-precharge current:
Burst = 4;
Address and control inputs changing once per clock cycle
Precharge power-down standby current: All banks idle;
Power-down mode;
Idle standby current: CS# = HIGH; All banks are idle;
t
inputs changing once per clock cycle; V
and DM
Active power-down standby current: One bank active;
Power-down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One bank
active;
inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
Operating burst read current: Burst = 2;
burst reads; One bank active; Address and control inputs
changing once per clock cycle;
Operating burst write current: Burst = 2; Continuous burst
writes; One bank active; Address and control inputs changing
once per clock cycle;
changing twice per clock cycle
Auto refresh burst current:
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four-bank
interleaving READs (burst = 4) with auto precharge;
t
control inputs change only during ACTIVE, READ, or WRITE
commands
CK =
CK =
RC = minimum
t
t
CK (MIN); DQ, DM, and DQS inputs changing once per
CK (MIN); CKE = HIGH; Address and other control
t
RC =
t
RC =
t
RAS (MAX);
I
V
0°C ≤ T
DD
DD
t
t
RC (MIN);
RC allowed;
Q = +2.6V ±0.1V, V
Specifications and Conditions (x4, x8: -5B, -6, -6T, -75E, -7Z, -75) - Die Revision F Only
t
t
A
t
CK =
CK =
CK =
≤ +70°C; Notes: 1–5, 11, 13, 15, 47; Notes appear on pages 35–40; See also Table 9 on page 18
t
t
t
CK =
t
t
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
CK =
CK (MIN); DQ, DM, and DQS inputs
t
CK =
t
CK =
t
CK (MIN); DQ, DM, and DQS
t
CK (MIN); I
t
CK (MIN); Address and
DD
t
CK (MIN);
IN
= +2.6V ±0.1V (-5B); V
= V
t
t
Standard
Low power (L)
REFC =
REFC =7.8µs
t
OUT
DD
RC =
REF
Continuous
I
= 0mA;
for DQ, DQS,
OUT
t
RC (MIN);
t
RFC (MIN)
= 0mA
17
DD
Q = +2.5V ±0.2V, V
Symbol
I
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
DD
4W
3N
5A
6A
2P
3P
4R
2F
0
1
5
6
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
-5B
135
170
200
195
260
470
60
40
70
4
6
4
2
256Mb: x4, x8, x16 DDR SDRAM
-6/6T -75E -75Z
125
170
175
175
255
410
50
30
60
DD
4
6
4
2
Electrical Specifications – I
= +2.5V ±0.2V (-6, -6T, -75E, -7Z, -75);
125
160
150
150
235
350
45
25
50
4
6
4
2
120
145
150
150
235
350
©2003 Micron Technology, Inc. All rights reserved.
45
25
50
4
6
4
2
120
145
150
150
245
365
-75
45
30
50
4
6
4
2
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
23, 48
23, 48
24, 33
24, 33
23, 48
28, 50
23, 49
51
23
23
50
12
12
DD