MT46V16M16P-5B:K Micron Technology Inc, MT46V16M16P-5B:K Datasheet - Page 85

DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.6V 66-Pin TSOP Tray

MT46V16M16P-5B:K

Manufacturer Part Number
MT46V16M16P-5B:K
Description
DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.6V 66-Pin TSOP Tray
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet

Specifications of MT46V16M16P-5B:K

Density
256 Mb
Maximum Clock Rate
400 MHz
Package
66TSOP
Address Bus Width
15 Bit
Operating Supply Voltage
2.6 V
Maximum Random Access Time
0.7 ns
Operating Temperature
0 to 70 °C
Organization
16Mx16
Address Bus
15b
Access Time (max)
700ps
Operating Supply Voltage (typ)
2.6V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.5V
Supply Current
260mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT46V16M16P-5B:K
Manufacturer:
MICRON
Quantity:
6 589
Part Number:
MT46V16M16P-5B:K
Manufacturer:
MICRON
Quantity:
20 000
Part Number:
MT46V16M16P-5B:K
Manufacturer:
MICRON
Quantity:
7 580
Figure 48:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Command
BA0, BA1
Address
DQS
DQ 5
CK#
CKE
A10
DM
CK
t
t
IS
IS
NOP 1
Bank WRITE – Without Auto Precharge
T0
t
t
IH
IH
Notes:
t
t
Bank x
IS
IS
Row
Row
ACT
T1
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. DI b = data-in from column b; subsequent elements are provided in the programmed order.
6. See Figure 50 on page 85 for detailed DQ timing.
t
t
IH
IH
t
times.
CK
t
t
RCD
RAS
NOP 1
T2
t
CH
t
CL
WRITE 2
t
Bank x
Col n
IS
3
T3
t
t
DQSS (NOM)
IH
t
WPRES
t DS
83
t
WPRE
NOP 1
T4
DI
b
t DH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T4n
t
DQSL
NOP 1
T5
t
DQSH
256Mb: x4, x8, x16 DDR SDRAM
T5n
t
WPST
NOP 1
T6
Transitioning Data
©2003 Micron Technology, Inc. All rights reserved.
t
NOP 1
WR
T7
Operations
One bank
All banks
Don’t Care
Bank x 4
T8
PRE
t
RP

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