MT46V16M16P-5B:K Micron Technology Inc, MT46V16M16P-5B:K Datasheet - Page 19

• Manufacturer Part Number: MT46V16M16P-5B:K
• Description: DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.6V 66-Pin TSOP Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V16M16P-5B:K

• Density: 256 Mb
• Maximum Clock Rate: 400 MHz
• Package: 66TSOP
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 2.6 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: 0 to 70 °C
• Organization: 16Mx16
• Address Bus: 15b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.6V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Supply Current: 260mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Table 8:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
256Mb_DDR_x4x8x16_D2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Parameter/Condition
Operating one-bank precharge current:
t
cycle; Address and control inputs changing once every two clock cycles
Operating one-bank active-read-precharge current: Burst = 4;
t
inputs changing once per clock cycle
Precharge power-down standby current: All banks idle; Power-
down mode;
Idle standby current: CS# = HIGH; All banks are idle;
CKE = HIGH; Address and other control inputs changing once per clock
cycle; V
Active power-down standby current: One bank active; Power-
down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One bank active;
t
twice per clock cycle; Address and other control inputs changing once
per clock cycle
Operating burst read current: Burst = 2;
One bank active; Address and control inputs changing once per clock
cycle;
Operating burst write current: Burst = 2; Continuous burst writes;
One bank active; Address and control inputs changing once per clock
cycle;
clock cycle
Auto refresh burst current:
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four-bank interleaving
READs (burst = 4) with auto precharge;
t
ACTIVE, READ, or WRITE commands
CK =
RC =
RC =
CK =
t
t
t
t
t
t
RC (MIN);
RAS (MAX);
CK (MIN); DQ, DM, and DQS inputs changing once per clock
CK (MIN); Address and control inputs change only during
CK =
CK =
IN
= V
t
t
CK (MIN);
CK (MIN); DQ, DM, and DQS inputs changing twice per
REF
t
t
I
V
0°C ≤ T
CK =
CK =
DD
DD
for DQ, DQS, and DM
t
CK =
Q = +2.6V ±0.1V, V
Specifications and Conditions (x4, x8, x16: -5B, -6, -6T) - Die Revision K Only
t
t
t
CK =
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
A
≤ +70°C; Notes: 1–5, 11, 13, 15, 47; Notes appear on pages 35–40; See also Table 9 on page 18
t
I
CK (MIN); I
OUT
t
CK (MIN); DQ, DM, and DQS inputs changing
= 0mA
OUT
DD
= 0mA; Address and control
= +2.6V ±0.1V (-5B); V
t
RC = minimum
t
RC =
Continuous burst reads;
t
RC (MIN);
t
t
t
Standard
Low power (L)
REFC =
REFC = 7.8µs
REFC = 1.95µs (AT)
t
CK =
t
RC allowed;
t
19
t
RFC (MIN)
CK (MIN);
DD
Q = +2.5V ±0.2V, V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
I
I
I
I
I
I
I
I
I
DD
DD
DD
DD
DD
I
I
DD
I
I
I
DD
DD
DD
DD
DD
DD
DD
DD
4W
3N
5A
5A
6A
4R
2P
2F
3P
0
1
5
6
7
256Mb: x4, x8, x16 DDR SDRAM
DD
Electrical Specifications – I
= +2.5V ±0.2V (-6, -6T);
-5B
100
120
180
180
160
290
50
35
60
4
6
9
4
2
©2003 Micron Technology, Inc. All rights reserved.
-6/6T
115
160
160
160
270
90
50
30
55
4
6
9
4
2
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
23, 48
23, 48
24, 33
24, 33
23, 48
28, 50
28, 50
23, 49
51
23
23
50
12
12
DD