MT46V16M16P-5B:K Micron Technology Inc, MT46V16M16P-5B:K Datasheet - Page 47

• Manufacturer Part Number: MT46V16M16P-5B:K
• Description: DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.6V 66-Pin TSOP Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V16M16P-5B:K

• Density: 256 Mb
• Maximum Clock Rate: 400 MHz
• Package: 66TSOP
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 2.6 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: 0 to 70 °C
• Organization: 16Mx16
• Address Bus: 15b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.6V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Supply Current: 260mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Table 31:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Current State
Any
Idle
Row activating, active,
or precharging
Read (auto precharge
disabled)
Write (auto precharge
disabled)
Read (with auto-
precharge)
Write (with auto-
precharge)
Truth Table 4 – Current State Bank n – Command to Bank m
Notes: 1–6 apply to the entire table; Notes appear on page 45
Notes:
CS#
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise, a
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of
1. This table applies when CKE
valid state for precharging.
bank.
precharge enabled and READs or WRITEs with auto precharge disabled.
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
after
• Refreshing: Starts with registration of an AUTO REFRESH command and ends when
• Accessing mode register: Starts with registration of an LMR command and ends when
• Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
RAS# CAS#
is met. Once
t
state.
t
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
MRD has been met. Once
RP is met. Once
t
XSNR has been met (if the previous state was self refresh).
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
t
RFC is met, the DDR SDRAM will be in the all banks idle state.
WE#
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
t
RP is met, all banks will be in the idle state.
Command/Action
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
n-1
45
t
MRD is met, the DDR SDRAM will be in the all banks idle
was HIGH and CKE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16 DDR SDRAM
n
is HIGH (see Table 33 on page 47) and
©2003 Micron Technology, Inc. All rights reserved.
Commands
Notes
7, 9
7, 8
7, 9
7
7
7
7
7
7
7
t
RFC