MT46V16M16P-5B:K Micron Technology Inc, MT46V16M16P-5B:K Datasheet - Page 92

• Manufacturer Part Number: MT46V16M16P-5B:K
• Description: DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.6V 66-Pin TSOP Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V16M16P-5B:K

• Density: 256 Mb
• Maximum Clock Rate: 400 MHz
• Package: 66TSOP
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 2.6 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: 0 to 70 °C
• Organization: 16Mx16
• Address Bus: 15b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.6V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Supply Current: 260mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Power-down (CKE Not Active)
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in
progress, from the issuing of a READ or WRITE command, until completion of the
access. Thus a clock suspend is not supported. For READs, an access completion is
defined when the read postamble is satisfied; for WRITEs, when the write recovery time
(
Power-down, as shown in Figure 55 on page 91, is entered when CKE is registered LOW
and all criteria in Table 33 on page 47 are met. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when a
row is active in any bank, this mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding CK, CK#, and CKE. For
maximum power savings, the DLL is frozen during precharge power-down mode. Exiting
power-down requires the device to be at the same voltage and frequency as when it
entered power-down. However, power-down duration is limited by the refresh require-
ments of the device (
While in power-down, CKE LOW and a stable clock signal must be maintained at the
inputs of the DDR SDRAM, while all other input signals are “Don’t Care.” The power-
down state is synchronously exited when CKE is registered HIGH (in conjunction with a
NOP or DESELECT command). A valid executable command may be applied one clock
cycle later.
t
WR) is satisfied.
t
REFC or
90
t
REFC
AT
).
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16 DDR SDRAM
©2003 Micron Technology, Inc. All rights reserved.
Operations