MT46V16M16P-5B:K Micron Technology Inc, MT46V16M16P-5B:K Datasheet - Page 89

• Manufacturer Part Number: MT46V16M16P-5B:K
• Description: DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.6V 66-Pin TSOP Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V16M16P-5B:K

• Density: 256 Mb
• Maximum Clock Rate: 400 MHz
• Package: 66TSOP
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 2.6 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: 0 to 70 °C
• Organization: 16Mx16
• Address Bus: 15b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.6V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Supply Current: 260mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Figure 52:
AUTO REFRESH
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Command
BA0, BA1
Address
DQS
CK#
CKE
A10
DQ
DM
CK
4
t IS
t IS
NOP
T0
Bank WRITE – with Auto Precharge
t IH
1
t IH
Notes:
t IS
t IS
Bank x
ACT
Row
Row
T1
t IH
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4.
3. Enable auto precharge.
4. DI n = data-out from column n; subsequent elements are provided in the programmed
5. See Figure 50 on page 85 for detailed DQ timing.
During auto refresh, the addressing is generated by the internal refresh controller. This
makes the address bits a “Don’t Care” during an AUTO REFRESH command. The DDR
SDRAM requires AUTO REFRESH cycles at an average interval of
To allow for improved efficiency in scheduling and switching between tasks, some flexi-
bility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH
commands can be posted to any given DDR SDRAM, meaning that the maximum abso-
lute interval between any AUTO REFRESH command and the next AUTO REFRESH
command is 9 ×
specifications exceed the JEDEC requirement by one clock. This maximum absolute
interval is to allow future support for DLL updates, internal to the DDR SDRAM, to be
restricted to AUTO REFRESH cycles, without allowing excessive drift in
updates.
t IH
times.
order.
t CK
t RCD
t RAS
NOP
T2
1
t CH
t
REFI(=
t CL
t IS
Bank x
3
WRITE
Col n
T3
t IH
t DQSS (NOM)
2
t
REFC). JEDEC specifications only support 8 ×
t WPRES t WPRE
t DS
87
NOP
T4
DI
b
1
t DH
T4n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DQSL
NOP
T5
t DQSH
1
256Mb: x4, x8, x16 DDR SDRAM
T5n
t WPST
NOP
T6
1
Transitioning Data
©2003 Micron Technology, Inc. All rights reserved.
t
REFI (MAX).
t WR
NOP
T7
1
t
t
REFI; Micron
AC between
Operations
Don’t Care
NOP
T8
1
t RP