MT46V16M16P-5B:K Micron Technology Inc, MT46V16M16P-5B:K Datasheet - Page 90

• Manufacturer Part Number: MT46V16M16P-5B:K
• Description: DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.6V 66-Pin TSOP Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V16M16P-5B:K

• Density: 256 Mb
• Maximum Clock Rate: 400 MHz
• Package: 66TSOP
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 2.6 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: 0 to 70 °C
• Organization: 16Mx16
• Address Bus: 15b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.6V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Supply Current: 260mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Figure 53:
SELF REFRESH
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Command
BA0, BA1
Address
DQS
DM
DQ
CK#
CKE
A10
CK
5
5
5
Auto Refresh Mode
NOP 1
t IS
t IS
T0
Notes:
t IH
t IH
One bank
All banks
Bank(s) 4
t IS t IH
PRE
Although not a JEDEC requirement, to provide for future functionality features, CKE
must be active (HIGH) during the AUTO REFRESH period. The AUTO REFRESH period
begins when the AUTO REFRESH command is registered and ends
1. NOP commands are shown for ease of illustration; other valid commands may be possible at
2. NOP or COMMAND INHIBIT are the only commands allowed until after
3. The second AUTO REFRESH is not required and is only shown as an example of two back-to-
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for the operations shown.
When in the self refresh mode, the DDR SDRAM retains data without external clocking.
The DLL is automatically disabled upon entering SELF REFRESH and is automatically
enabled upon exiting SELF REFRESH (a DLL reset and 200 clock cycles must then occur
before a READ command can be issued). Input signals except CKE are “Don’t Care”
during SELF REFRESH. V
REFRESH.
The procedure for exiting SELF REFRESH requires a sequence of commands. First, CK
and CK# must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for
completion of any internal refresh in progress. A simple algorithm for meeting both
refresh and DLL requirements is to apply NOPs for
T1
these times. CKE must be active during clock-positive transitions.
be active during clock-positive transitions.
back AUTO REFRESH commands.
(that is, must precharge all active banks).
CK
NOP 1
Valid
T2
t CH
t RP
t CL
NOP 1
T3
REF
voltage is also required for the full duration of SELF
AR
88
T4
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t RFC
NOP 1,2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Ta0
t
XSNR because time is required for the
256Mb: x4, x8, x16 DDR SDRAM
AR 3
Ta1
t
XSRD time, then a DLL RESET (via
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NOP 1,2
Valid
Tb0
©2003 Micron Technology, Inc. All rights reserved.
t RFC
t
RFC later.
NOP 1
Tb1
t
RFC time; CKE must
Operations
Don’t Care
Tb2
ACT
BA
RA
RA