W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet

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W83C553FY-G

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W83C553FY-G
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Nuvoton Technology Corporation of America
Datasheet

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W83C553FY-G Summary of contents

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W83C553F 1.3 Stylistic Conventions Used in this Manual The following stylistic conventions have been used throughout this manual: • Signal names: Signals that are active at a low voltage level are indicated by a pound sign (#) after the signal ...

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W83C553F 2.0 PIN DESCRIPTIONS This chapter shows the pin diagrams, pins listed by pin number, device logic symbols, and describes each pin signal for the W83C553F. 2.1 Pin Assignments Figure 2-1. Pin Assignments for the W83C553F WINBOND SYSTEMS LABORATORY Pin ...

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W83C553F Table 2-1. W83C553F Pins Listed by Pin Number 1 DRQ7 2 PWRGD 3 INIT 4 IGNNE#/HRESET# 5 PMACT#/ISARST 6 GNT4#/FLSHREQ# 7 REQ4#/FLSHACK# 8 PWRPC/X86#/CPUGNT# 9 CPUREQ# 10 INT 11 NMI 12 FERR#/IRQ13 13 PCI5TH#/GNT3# 14 VDD 15 REQ3# 16 ...

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W83C553F Note: Pins direction and assignment may not reflect exact pins , refers to exact pin description . Figure 2-2. W83C553F Logic Symbol Diagram WINBOND SYSTEMS LABORATORY Pin Descriptions 12 ...

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W83C553F 2.2 Pin Descriptions This section describes the location and function of each pin on the W83C553F. Note the following conventions used in the tables: • Where more than one pin is listed for a signal, the first pin number ...

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W83C553F Pin Name Pin # PCICLK 23 A20M PCIRST# AD[31:0] 29-31,33-37,41- 44, 46,47, 49, 50, 62-67, 69,71,73 - 79,81 C/BE[3:0]# 39, 51, 61, 72 PAR 60 WINBOND SYSTEMS LABORATORY Table 2-2. PCI Bus Signals Input/ Output Description Input ...

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W83C553F Pin Name Pin # FRAME# 53 PERR# 58 IRDY# 54 TRDY# 55 DEVSEL# 56 STOP# 57 IDSEL 40 SERR# 59 WINBOND SYSTEMS LABORATORY Table 2-2 (Continued). PCI Bus Signals Input/ Output Description Input/ Cycle Frame. Indicates the start and ...

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W83C553F Pin Name Pin # INT[A:B]# 21-20 INT[C:D]# 19-18 LOCK# 52 WINBOND SYSTEMS LABORATORY Table 2-2 (Continued). PCI Bus Signals Input/ Output Description Input PCI Interrupts. These PCI interrupts can be routed to the programmable interrupt controller inside the W83C553F ...

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W83C553F Pin Name Pin # GNT0 PIBREQ# REQ0 PIBGNT# GNT1 IDEREQ# REQ1 IDEGNT# 16 ARBDIS# / GNT2# REQ2# 17 WINBOND SYSTEMS LABORATORY Table 2-3. PCI Arbiter Signals Input/ Output Description Output This ...

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W83C553F Pin Name Pin # 13 PCI5TH# / GNT3# REQ3# 15 GNT4 FLSHREQ# REQ4 FLSHACK# 8 PWRPC/X86# / CPUGNT# CPUREQ# 9 WINBOND SYSTEMS LABORATORY Table 2-3 (continued). PCI Arbiter Signals Input/ Output Description Input/ When the ...

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W83C553F Pin Name Pin # IDECS0 IDECS1#/ NAT/LEG# IDEIOWA# 85 IDEIORA# 83 IDEIOWB# 84 IDEIORB# 82 WINBOND SYSTEMS LABORATORY Table 2-4. IDE Interface Bus Signals Input/ Output Description Output Drive Chip Select 0. This signal is decoded from ...

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W83C553F Pin Name Pin # IDEDRQA 97 IDEDAKA# 94 IDEDRQB 96 IDEDAKB# 93 DA[2:0] 88,90,89 DD[15:0] 98,101,103, 105,108, 110,112, 114,115, 113,111, 109,106, 104,102, 100 IDECHRDY 95 IDEIRQB 91 IDEIRQA 92 WINBOND SYSTEMS LABORATORY Table 2-4 (continued). IDE Interface Bus Signals ...

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W83C553F Pin Name Pin # BCLK 200 OSC 172 LA[23:17] 176,178, 180,182, 184,187, 189 SA[16:0] 144,145, 147-149, 151,152, 155,158, 160,162, 164,165, 167,169, 171,173 MASTER# 143 REFRESH# 150 MEMR# 141 MEMW# 142 WINBOND SYSTEMS LABORATORY Table 2-5. ISA Bus Signals Input/ ...

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W83C553F Pin Name Pin # IOR# 140 IOW# 139 SMEMR# 138 SMEMW# 137 ZWS# 132 SBHE# 174 M16# 175 IO16# 177 IOCHK# 122 WINBOND SYSTEMS LABORATORY Table 2-5 (Continued). ISA Bus Signals Input/ Output Description Input/ I/O Read. Act as ...

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W83C553F Pin Name Pin # IOCHRDY 135 BALE 168 AEN 136 TC 166 DRQ[7:5, 3:0] 1,203,198, 191,190, 193,196 DAK[2:0] 194,192, 195 IRQ[15, 14, 12:9, 186,188, 7:3] 183,181, 179,127, 154,157, 159,161, 163 WINBOND SYSTEMS LABORATORY Table 2-5 (Continued). ISA Bus Signals ...

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W83C553F Pin Name Pin # PMACT ISARST SD[15:0] 208-204, 202,199, 197,123, 125,126, 128-131, 133 WINBOND SYSTEMS LABORATORY Table 2-5 (Continued). ISA Bus Signals Input/ Output Description Output This multi-function pin functions as ISA Reset when the W83C553F is ...

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W83C553F Pin Name Pin # 116 SECURITY / XRD# IRQ1 121 IRQ8# 120 117 XOE# XCS0/ 119 ROMCS XCS1/X8XCS 118 WINBOND SYSTEMS LABORATORY Table 2-6. X Bus Signals Input/ Output Description Output/ X Bus Read. When active "0", data flows ...

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W83C553F Table 2-7. CPU Interface and Miscellaneous Signals Pin Name Pin # INT 10 NMI 11 INIT 3 SPKR 134 PWRGD 2 FERR#/IRQ13 12 IGNNE HRESET# WINBOND SYSTEMS LABORATORY Input/ Output Description Output Interrupt. Interrupt signal from the ...

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W83C553F Pin Name Pin # VSS 24,38,48, 68,80, 107,124, 146,156, 170,201 VDD 14,32,45, 70,99,153,185 WINBOND SYSTEMS LABORATORY Table 2-8. Power and Ground Signals Input/ Output Description - These 11 pins are connected to the power supply ground. All VSS pins ...

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W83C553F 3.0 SYSTEM ARCHITECTURE 3.1 Overview The W83C553F is a multi-function PCI device. "Function 0" is the PCI-to-ISA bridge logic; "Function 1" is the bus master IDE controller. Each function has its own separate PCI configuration space and I/O register ...

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W83C553F The IDE interface is fully ANSI CAM compliant to the ATA Revision 3.0 and the ATA-2 specifications. Each storage device on the two ports is individually programmable to select the desired command on and off times to support ATA ...

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W83C553F Four basic data paths are provided. One provides the timing and control functions for 8-bit I/O cycles that communicate control/status information with the IDE devices. A second data path provides the timing and control functions for 16-bit and 32-bit ...

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W83C553F 3.4 PCI-to-ISA Bridge The W83C553F PCI System I/O provides the PCI bus interface functions. It contains both PCI master and slave bus bridging. When PIBGNT# is asserted, the master bridge translates an ISA master or DMA cycle to the ...

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W83C553F The next rising clock edge identifies the beginning of the data phase. Address parity is valid and will be checked or ignored depending on the state of the SE bit of the Device Control Register. The data phase can ...

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W83C553F Refer to Figure 3-1. Bus acquisition timing cycles are defined by the C/BE[3:0]# command lines during the address (AD) phase of each PCI cycle. WINBOND SYSTEMS LABORATORY Figure 3-1. Bus Acquisition Timing Electrical Specifications 33 ...

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W83C553F 3.6 PCI I/O Read Cycle Bursting is not supported by the W83C553F for I/O cycles target disconnect will be executed after the first data transfer on all I/O Read commands to prevent multiple I/O data phases. Refer ...

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W83C553F 3.7 PCI I/O Write Cycle Bursting is not supported by the W83C553F for I/O cycles target disconnect will be executed after the first data transfer on all I/O Write commands to prevent multiple I/O data phases. Refer ...

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W83C553F 3.8 PCI Configuration Read Cycle The Configuration Read command (C/BE[3:0 during address phase) is used in slave mode to read the configuration registers. 8-bit, 16-bit, 24-bit and 32-bit accesses are supported when the IDSEL is asserted and ...

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W83C553F 3.9 PCI Configuration Write Cycle The Configuration Write command (C/BE[3:0 during address phase) is used in slave mode to write to the configuration registers. 8-bit, 16-bit, 24-bit and 32-bit accesses are supported when the IDSEL is asserted ...

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W83C553F 3.10 PCI Memory Read The Memory Read command (C/BE[3:0 during the address phase) is only used when operating as a bus master. It will be used when transferring data to memory and the number of data phases ...

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W83C553F 3.11 PCI Memory Write The Master Memory Write command (C/BE[3:0 during the address phase) cycle is used by the W83C553F when writing to memory. The W83C553F issues a request for the bus and, when granted access, writes ...

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W83C553F 3.12 PCI Memory Read Line The Memory Read Line command (C/BE[3:0 during the address phase) is only used when operating as a bus master. It will be used when transferring data to memory and the number of ...

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W83C553F 3.14 Transaction Termination The termination of a PCI transaction can be initiated by either the master or target. During termination, the master controls the completion of all PCI transactions, regardless of what caused the termination. All transactions are concluded ...

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W83C553F 3.14.2 PCI Disconnect Without Data Transfer Timing The Disconnect Without Data Transfer command cycle of Figure 3-10 shows a target disconnect when no data is transferred. STOP# is asserted without TRDY# being asserted at the same time. The W83C553F ...

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W83C553F 3.14.3 PCI Target Abort Timing The Target Abort cycle of Figure 3-11 starts when the target asserts DEVSEL# for one clock, then de-asserts DEVSEL# and asserts STOP#. A target can use this sequence to indicate it cannot service the ...

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W83C553F 3.14.4 PCI Preemption Timing The main arbiter can void the PCI GNT# signal sent to the W83C553F, if the current bus cycle takes too long the case of DMA bursts. When PCI GNT# is removed, and the ...

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W83C553F 3.14.5 PCI Master Abort Timing A Master Abort sequence is initiated by the W83C553F to abort its cycle if DEVSEL# is not asserted within four clocks after FRAME# is asserted. This sequence is treated as a fatal error. Any ...

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W83C553F 3.15 IDE Interface Operation Operation of the IDE interface is controlled by the configuration registers. Port 0 (Primary Port) and Port 1 (Secondary Port) have the same features, capabilities and configuration options. All 8-bit timing is fixed. The following ...

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W83C553F 3.16 PIO Transfers When transferring data with the PIO protocol, I/O read/write cycles are executed on the IDE interface and PIO transfers are executed on the PCI bus. The IDE interface address and chip select signals will only change ...

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W83C553F 3.17 32-Bit Data Transfers 32-bit data transfers are used to reduce system overhead and improve performance. The standard PIO protocol requires the system CPU to execute an I/O cycle and a memory cycle to move two bytes of data ...

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W83C553F 3.18 Bus Master Transfers When operating as a bus master on the PCI bus, DMA cycles will be executed on the IDE interface. In this mode, once the BMEN bit of the Bus Master Control Register is set the ...

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W83C553F 3.21 82C54 Counter/Timer One 82C54 counter/timer, with three channels, is included in the W83C553F. The clocks for the three channels are connected to the 14.31818 MHz clock through a divide-by-twelve counter. The gate inputs of counters 0 and 1 ...

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W83C553F 3.23 Break Events Break events include IRQ0 - IRQ15, DRQ0 - DRQ7, SERR#, ISA IOCHK#, INTR and non-maskable interrupts to the CPU (NMI). OEM designers can program Function 0 PCI Configuration Registers 60h - 63h to select individual IRQs ...

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W83C553F 4.0 REGISTER INFORMATION The W83C553F SIO controller with PCI arbiter is a multi-function PCI device. Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller. The registers summarized in this section are organized as ...

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W83C553F W83C553F Register Accessibility Functional Block Config. Space PIC 1 Counter/Timer Port B RTC Index (shadow) DMA Page Port 92 PIC2 Co-processor Error DMA1 BMTR DMA2 Interrupt Mode RTC CMOS RAM X = accessible in x86 mode P = accessible ...

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W83C553F 4.1 PCI Configuration Space - ISA Bridge Registers (Function 0) 4.1.1 Function 0 Header Registers Vendor ID Register (default = 10ADh) Bit Description: Bits [15:0]: VENDID. Vendor ID for Symphony Laboratories is 10ADh. Device ID Register (default = 0565h) ...

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W83C553F Command Register (default = 0007h) Type: Read/Write Bit Description: Bits [15:10]: Reserved. These read only bits are all set to "0". Bit 9: Fast Back-to-Back Enable. W83C553F does not generate fast back-to-back cycles. This read only bit is set ...

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W83C553F Status Register (default = 0200h) Type: Read/Write Bit Description: Bit 15: Detected Parity Error (DPE). This bit is read/write. Bit 14: Signaled System Error (SSE). Bit 13: Received Master Abort (RMA). This bit is read/write. Bit 12: Received Target ...

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W83C553F Revision ID Register (default = 00h) Bit Description: Bits [7:0]: REVID. Revision ID for ISA Bridge is 00h. Class Code Register (default = 060100h) Bit Description: Bits [23:16]: BCLASS. Base Class is 06h. Bridge device. Bits [15:8]: SCLASS. Sub-Class ...

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W83C553F 4.1.2 Function 0 Control Registers PCI Control Register (default = 20h) Type: Read/Write Bit Description: Bit 7: Reserved. This read only bit is set to "0". Bit 6: Reserved. Bit 5: IAE. Interrupt Acknowledge Enable. Setting this bit allows ...

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W83C553F Scatter/Gather Relocation Base Address Register (default = 04h) Function: The value programmed into this register determines the high order I/O adress of the Scatter/Gather Command Registers, Scatter/Gather Status Registers, and Scatter/Gather Descriptor Table Registers. The first Scatter/Gather register default ...

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W83C553F Line Buffer Control Register (default = 00h) Type: Read/Write Bit Description: Bits [7:4]: Reserved. Bits [3:2]: ISA Master Line Buffer Configuration. Bit Bits [1:0]: DLBC. DMA Line Buffer Configuration. ...

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W83C553F PCI Interrupt Routing Control Register (default = 0000h) Type: Read/Write Bit Description: Bits [15:12]: INTARCH [3:0]. INTA# Routing Channel. This field specifies the routing channel for INTA#. Note channels and 13 are reserved. Setting this ...

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W83C553F BIOS Timer Base Address Register (default = 0078h) Type: Read/Write Function: The base address for the BIOS Timer Register located in PCI I/O space. The BIOS Timer resides in the W83C553F and is the only internal resource mapped to ...

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W83C553F ISA-to-PCI Address Decoder Control Register (default = 01h) Type: Read/Write Bit Description: Bits [7:4]: IPATOM [3:0]. Top of Main Memory. Defines the top of memory for ISA memory space. ISA memory accesses from 1 MByte to top of memory ...

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W83C553F ISA ROM Address Decode Enable Register (default = 00h) Function: When a bit is set to "1", memory accesses to the corresponding address range in the add-on BIOS area are forward to the PCI bus. Type: Read/Write Bit Description: ...

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W83C553F ISA-to-PCI Memory Hole Start Address Register (default = 00h) Type: Read/Write Bit Description: Bits [7:0]: IPAHA. Memory Hole Start Address. These 8 bits specify the 8 most significant bits of the ISA address: LA[23:16]. Bit 7 Bit 6 LA23 ...

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W83C553F Clock Divisor Register (default = 00h) Type: Read/Write Bit Description: Bits [7:4]: Reserved. Bit 3: RSTDRV. Reset Drive, valid only in PowerPC mode. When this bit is set, PCIRST# and ISARST are enabled for 1 ms. This bit then ...

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W83C553F Chip Select Control Register (default = 33h) Type: Read/Write Bit Description: Bit 7: EBIOSCSE. Extended BIOS Enable. 0= Disabled 1= Memory access from FFF80000h to FFFDFFFFh will assert ROMCS in PowerPC mode or the encoded output XCS[1 ...

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W83C553F AT System Control Register (default = 04h) Type: Read/Write Bit Description: Bit 7: Reserved. Bit 6: ISA Refresh Enable. Bit 5: Reserved, always 0. Bit 4: FERR# Enable. If this bit is set to "1," pin 12 will function ...

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W83C553F AT Bus Control Register (default = 00h) Type: Read/Write Bit Description: Bits [7:3]: Reserved. Bit 2: I/O Recovery Time normal BCLK delay for 16-bit I/O and 8 BCLK for 8-bit I/O access Bit 1: ...

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W83C553F IRQ Break Event Enable 0 Register (default = 00h) Function: This power management register may only be used while the W83C553F is in x86 mode. Type: Read/Write Bit Description: Bit 7: IRQ7. Enable IRQ7 as Break Event. When this ...

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W83C553F IRQ Break Event Enable 1 Register (default = 00h) Function: This power management register may only be used while the W83C553F is in x86 mode. Type: Read/Write Bit Description: Bit 7: IRQ15. Enable IRQ15 as Break Event. When this ...

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W83C553F Additional Break Event Enable Register (default = 00h) Function: This power management register may only be used while the W83C553F is in x86 mode. Type: Read/Write Bit Description: Bit 7: Reserved. Bit 6: PCI SERR#. SERR Detection Enable. When ...

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W83C553F DMA Break Event Enable Register (default = 00h) Function: This power management register may only be used while the W83C553F is in x86 mode. Type: Read/Write Bit Description: Bit 7: DRQ7. Enable DRQ7 as Break Event. When this bit ...

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W83C553F Level 1 Arbiter There are two control bits for bank 1,2,3 modules. The "pfix" bit determines the fixed priority of the bank. The "protat" bit determines whether to rotate the priority scheme of the bank after a grant is ...

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W83C553F Function: These register locations are reserved. Software should not attempt to read or write these locations. PCI Arbiter Priority Control Register 1 (default = E0h) Type: Read/Write Bit Description: Bits [7:5]: Bank [3:1] Rotate Enable. Defaults to 111b (enabled). ...

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W83C553F PCI Arbiter Priority Extension Control Register PCI Arbiter Priority Extension Control Register (default = 01h) Type: Read/Write Bit Description: Bits [7:4]: Reserved Bits [3:1]: Super Agent Select [2:0]. 000 DISABLE 001 IDEIRQ# 010 SIOIRQ# 011 CPUREQ# Bits 0: Bank ...

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W83C553F PCI Arbiter Control Register (default = 80h) Type: Read/Write Bit Description: Bit 7: GAT. Guaranteed Access Timing. If set to a 1b, this bit enables Function 0 Flush Request and Flush Acknowledge operation on pins 6 and 7 (provided ...

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W83C553F 4.2 ISA Bridge (Function 0) I/O Registers 4.2.1 DMA Controller I/O Registers Base and Current Address Register Type: Read/Write Bit Description: Bits [15:0]: Base and Current Address. Access by two consecutive cycles. Internal high/low byte pointer toggles after each ...

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W83C553F DMA Command Register (default = 00h) Type: Write only Bit Description: Bit 7: Reserved. Bit 6: DRQ Active Level. When this bit is "0" (default), DRQ is active high. When this bit is "1," DRQ is active low. Bit ...

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W83C553F DMA Controller 1 Status Register (default = 00h) Type: Read only Bit Description: Bit 7: Channel 3 Request. Bit 6: Channel 2 Request. Bit 5: Channel 1 Request. Bit 4: Channel 0 Request. Bit 3: Channel 3 Terminal Count. ...

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W83C553F DMA Controller 2 Status Register Type: Read only Bit Description: Bit 7: Channel 7 Request. Bit 6: Channel 6 Request. Bit 5: Channel 5 Request. Bit 4: Reserved. Cascade for DMA Controller 1. Bit 3: Channel 7 Terminal Count. ...

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W83C553F DMA Controller Request Register Type: Write only Bit Description: Bits [7:3]: Reserved. Bit 2: Set Request. Bits [1:0]: Channel Select. DMA Controller Mask Register Type: Write only Bit Description: Bits [7:3]: Reserved. Bit 2: SETMASK. Set Mask bit. Bits ...

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W83C553F DMA Controller Mode Register Type: Write only Bit Description: Bits [7:6]: Transfer Mode. Bit 7 Bit Bit 5: Decrement Address. When set to "1", address pointer is decremented after each ...

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W83C553F Clear Byte Pointer Register Type: Write only Bit Description: Bits [7:0]: Clear Byte Pointer. Writing any pattern in this register will reset the byte pointer for the Base and Current Address/Data registers. Master Clear Register Type: Write only Bit ...

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W83C553F Clear Mask Register Type: Write only Bit Description: Bits [7:0]: Reserved. Writing this register will clear the mask bits of all channels. Write All Mask Register (default = 0Fh) Type: Write only Bit Description: Bits [7:4]: Reserved. Bit 3: ...

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W83C553F Memory Page Register (default = 00h) Type: Read/Write Bit Description: Bits [7:0]: Memory Address [23:16] for DMA cycles. Reserved Page Register Bit Description: Bits [7:0]: Reserved. Software should not attempt to access these registers. WINBOND SYSTEMS LABORATORY Electrical Specifications ...

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W83C553F Extended Mode Register (default = 0xh) Type: Write only Bit Description: Bits [7:6]: Reserved. Bits [5:4]: Timing. Bit 5 Bit Bits [3:2]: Reserved. Bits [1:0] DMAC[1:0] Channel Select. Bit 1 Bit ...

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W83C553F WINBOND SYSTEMS LABORATORY Electrical Specifications 88 ...

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W83C553F Scatter/Gather Registers Scatter/Gather (S/G) provides the capability of transferring multiple buffers between memory (ISA/PCI) and I/O (ISA DMA device) without CPU intervention. In Scatter/Gather the DMA can read the memory address and word count from an array of buffer ...

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W83C553F Scatter/Gather Interrupt Status Register Scatter/Gather Interrupt Status Register (default = 00h) Type: Read only Bit Description: Bits [7:5]: Channel [7:5] Interrupt Status. When one of these bits is set to a 1b, Channels 7 through 5 have an interrupt ...

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W83C553F Scatter/Gather Command Registers (default = 000000h) Function: Each of these three registers controls the Scatter/Gather operation of DMA channels [7:5]. Type: Write only Bit Description: Bit 7: IR13EOPSEL. IRQ13/EOP Select. If enabled via bit 6 of this register, bit ...

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W83C553F Scatter/Gather Status Registers Type: Read only Bit Description: Bit 7: NEXT_LINK_NULL. Next Link Null Indicator. Bit 6: Reserved. Bit 5: ISSUE_IRQ13_EOP. Issue IRQ13 on last buffer. When bit EOP is issued on last buffer; when bit ...

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W83C553F Scatter/Gather Descriptor Table Pointer Register Type: Read/Write Bit Description: Bits [31:0]: SG_TBL_PTR. The Scatter/Gather Descriptor Table Pointer Register contains a 32-bit pointer address to the main memory location where the software maintains the Scatter/Gather descriptors for the linked-list buffers. ...

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W83C553F 4.2.2 Programmable Interrupt Controller (PIC) Registers Initialization Command Word 1 Register (default = 19h) Function: A write to the Initialization Command Word 1 (ICW1) Register starts the interrupt controller initialization sequence. Addresses 20h and A0h are referred to as ...

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W83C553F Operational Control Word 2 Register Function: The Operational Control Word 2 (OCW2) Register controls both the Rotate Mode, End of Interrupt Mode and combinations of the two. Type: Write Only Bit Description: Bits [7:5]: ROT, SELLEVEL and EOI. These ...

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W83C553F Operational Control Word 3 Register Function: The Operational Control Word 3 (OCW3) Register serves three functions. It enables special mask mode and controls poll mode and IRR/ISR register read. Type: Read/Write Bit Description: Bit 7: Reserved. This bit must ...

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W83C553F Initialization Command Word 2 Register Function: The Initialization Command Word 2 (ICW2) Register is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address. The value programmed into bits [7:3] is used ...

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W83C553F Initialization Command Word 3 Register - PIC 1 (Master, default = 04h) Function: On the Interrupt Controller #1 (the master controller), this register indicates which IRQ line physically connects the INT output of Interrupt Controller #2 (PIC 2) to ...

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W83C553F Initialization Command Word 4 Register Function: Both interrupt controllers must have the Initialization Command Word 4 (ICW4) Register programmed as part of their initialization sequence minimum, bit 0 must be set to "1" to indicate it is ...

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W83C553F Operational Control Word 1 Register Function: The Operational Control Word 1 (OCW1) Register sets and clears the mask bits in the Interrupt Mask (IMR) Register. Each interrupt request line may be selectively masked or unmasked any time after initialization. ...

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W83C553F Interrupt Edge/Level Control Register (default = 00h) Type: Read/Write Bit Description: Bit 7: Controller 1-Channel 7. Controller 2-Channel 15. Bit 6: Controller 1-Channel 6. Controller 2-Channel 14. Bit 5: Controller 1-Channel 5. Controller 2-Channel 13; must be "0" for ...

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W83C553F 4.2.3 Counter/Timer I/O Registers Counter Register Function: These three registers contain the actual counter values programmed into counters 0 through 2. The set values are determined by selections made in the Timer Control Register (43h). Type: Read/Write Bit Description: ...

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W83C553F Counter Status Register Function: Each counter's status byte can be read following a timer Read Back command, as programmed in the Timer Control Register (43h). Type: Read back Bit Description: Bit 7: OUT. Count Out Status. This bit indicates ...

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W83C553F Timer Control Register Function: The Timer Control Register specifies the counter selection, operating mode, counter byte programming order and count value size, and whether the counter counts down in a 16-bit or Binary Coded Decimal (BCD) format. After writing ...

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W83C553F BIOS Timer Register (default = 00000000h) Function: After a counter value is written into the lower 16 bits of this register, it will decrement to 0 with every BCLK. Type: Default Bit Description: Bits [31:16]: Reserved. Bits [15:0]: BTMR. ...

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W83C553F 4.2.4 Miscellaneous I/O Control Registers NMI Status and Control (Port B) Register (default = 00h) Type: Read/Write Bit Description: Bit 7: SERR# Status. Bit 6: IOCHK# Status. Bit 5: Timer Counter 2 Output. Bit 4: Refresh Cycle Toggle. Bit ...

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W83C553F NMI Enable and RTC Address Register (default = 0xxx, xxxx) Type: Shadow Bit Description: Bit 7: NMI Enable. Bits [6:0]: RTC Address. WINBOND SYSTEMS LABORATORY Electrical Specifications Share 107 ...

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W83C553F Port 92 Register (default = 24h) Type: Read/Write Bit Description: Bits [7:3]: Reserved. These bits default to "00100." Bit 2: Read only. Value of pin 116 after reset. See page 25. Bit 1: Alt A20. Bit 0: Hot Reset. ...

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W83C553F RTC CMOS RAM Protect 1 Register Type: Write only Bit Description: Bits [7:0]: Any value. Writing any value to this port sets a flip-flop which prevents any subsequent access to addresses 20h - 2Fh of the Real Time Clock ...

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W83C553F 4.3 PCI Configuration Space - Bus Master IDE Registers (Function 1) The configuration space is organized as 64 double word (32-bit) registers divided into two sections, the PCI specified and defined Header registers and the Control registers. ...

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W83C553F Table 4-2. Organization of IDE Control Registers Address 31 43h-40h IDE Control/Status Register 47h-44h Port 0 Drive 0 Control Register 4Bh-48h Port 0 Drive 1 Control Register 4Fh-4Ch Port 1 Drive 0 Control Register 53h-50h Port 1 Drive 1 ...

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W83C553F 4.3.1 Function 1 Header Registers The registers contained in this address space are defined and required by the PCI Specification Revision 2.1. Six fields in the pre-defined header deal with device identification. These fields are Vendor ID, Device ID, ...

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W83C553F Device Control Register (default = 0000h) Function: The Device Control Register provides coarse control over the device's ability to generate and respond to I/O cycles. Since the default value disables the IO decode, it must be programmed by the ...

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W83C553F Bit 4: MWIEN. When this bit is 1b, Memory write and invalidate commands are enabled, when acting as a bus master. When this bit is 0b, only memory writes can be used. This bit after a ...

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W83C553F Device Status Register (default = 0280h) Function: The Device Status Register is used to record status information for PCI bus related events. Reads to this register behave normally. Writes report slightly different, in that bits can be reset, but ...

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W83C553F Bit [10:9] DSTMG. These bits encode the timing of DEVSEL#. They are hardwired to 01b indicating the support of medium DEVSEL# timing. This allows for support of fast back-to-back PCI bus cycles. This will maximize the PCI bus bandwidth ...

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W83C553F Revision ID Register (default = 05h) Function: This register specifies a device specific revision identifier. The first Symphony bus master device was 01h with subsequent bus master IDE chips being 02h, 03h, etc. This specification is written to define ...

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W83C553F Programming Interface Register ( Default = 8Ah) Function: There are no PCI predefined configuration register sets released for this class of device but the PCI SIG has generated two proposed interfaces which are both supported. The first interface defines ...

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W83C553F PCI Base and Sub Class Register (default = 0101h) Type: Read only Bit Description: Bits [15:8]: Sub Class. Permanently defaults to 01h - “IDE Controller.” Bits [7:0]: Base Class. Permanently defaults to 01h - “Mass Storage Controller.” Cache Line ...

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W83C553F Latency Timer Register (default = 00h) Function: This register specifies, in PCI bus clocks, the value of the latency timer when operating as a bus master. Bits 0 through 2 are hardwired to a 0b. Bits 3 through 7 ...

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W83C553F Base Address Registers 0 through 3 (10h-13h, 14h-17h, 18h-1Bh, 1Ch-1Fh) The W83C553F can be configured to support these Base Address Registers or to disable them. This can be useful in configuring the device to operate in PCI systems that ...

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W83C553F Base Address Register 4 (20h-23h) This Base Address Register is used to define the I/O address of the Bus Master IDE Register set in systems which use multi- word DMA mode disk drives. This register set is internal to ...

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W83C553F Min. Grant (3Eh) and Max. Latency (3Fh) Registers These read-only registers specify the desired latency timer value. They each represent a number of 1/4 microsecond time units. The Min Grant is the time required to complete a worst case ...

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W83C553F 4.3.2 Function 1 Control Registers These configuration registers control various features of the W83C553F and the IDE interface. Reserved registers are hardwired to a 00h and cannot be programmed. The first register controls the general features of the W83C553F ...

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W83C553F IDE Control/Status Register Function: This register controls the two IDE ports of the W83C553F. Type: Read/Write WINBOND SYSTEMS LABORATORY Electrical Specifications 125 ...

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W83C553F Bit Description: Bit 31: Reserved. This bit is hardwired to 0b. Bit 30: IDE_IRQB. This is the IDE_IRQB input signal. It reflects the unbuffered state of the IDE_IRQB input. Bit 29: Reserved. This bit is hardwired to 0b. Bit ...

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W83C553F Port x Drive x Control Registers Function: These registers control the features of the four devices connected to the two ports. All four registers are identical and control the features of only one device. The Port 0 Drive 0 ...

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W83C553F Type: Read/Write Bit Description: Bits [31:24]: Reserved. These bits are hardwired to a 0b. Bits [23:16]: User Defined. These bits are read/write and do not affect the operation of the W83C553F. They can be used by the driver as ...

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W83C553F Table 4-4. Programming CMD ON and CMD OFF Times Drive Operation Cycle Time / Mode DIOR#/DIOW# 16-bit (minimum) PIO Mode 0 600ns/165ns PIO Mode 1 383ns/125ns PIO Mode 2 240ns/100ns PIO Mode 3 PIO Mode 4 PIO Mode 5 ...

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W83C553F 4.4 Bus Master IDE (Function 1) I/O Registers The Bus Master IDE Register set is defined by the PCI SIG composed of 16 8-bit registers and is located at the I/O address specified by Base Address Register ...

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W83C553F 4.4.1 Primary/Secondary Command Registers Primary/Secondary Command #1 Registers Function: These registers are used to control DMA data transfers to/from the two IDE ports when multi-word DMA disk drives are used. Type: Read/Write Bit Description: Bits [7:4]: These bits are ...

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W83C553F 4.4.2 Primary/Secondary Status Registers Primary/Secondary Status #1 Registers (default = 00h) Function: These register descriptions are the same and are used to control the two IDE ports under the protocol, which requires a multi-word DMA-capable disk drive in order ...

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W83C553F 4.4.3 Primary/Secondary PRD Table (Base Address Register 4 value + offset: 07h-04h, 0Fh-0Ch) These registers contain the starting address of the first Physical Region Descriptor Table in memory which applies to cases where the W83C553F is functioning as a ...

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W83C553F 5.0 ELECTRICAL SPECIFICATIONS This section contains all electrical specifications for Winbond Systems Laboratory W83C553F SIO chip. The W83C553F must meet all absolute maximum ratings to avoid being damaged; and all combinations of the AC, DC and recommended operating specifications. ...

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W83C553F Table 5.3. DC Characteristics (Ta=0°C to 70°C, Vdd=5V+/-5%) Parameter Input low level Input high level Output low voltage: 4mA buffer, IOL=4mA 8mA buffer, IOL=8mA 12mA buffer, IOL=12mA 16mA buffer, IOL=16mA Output high voltage: 4mA buffer, IOL=4mA 8mA buffer, IOL=8mA ...

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W83C553F 6.0 TIMING DIAGRAMS This chapter lists the following PCI, ATA, and ISA timing information: • PCI Clock Timing • PCI Bus Timing • IDE Interface Timing • IDE Data Transfer Timing • Miscellaneous Timing • Example PIO ATA Data ...

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W83C553F 6.1 PCI Timing Diagrams This section provides timing information on PCI cycles supported by the W83C553F. Note: For 5V PCI Bus, measurements were taken from 0.4V to 2.4V. All V DD are 4.75V to 5.25V Parameter t1 CLK cycle ...

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W83C553F Note: For 5V PCI Bus, measurements were taken from 0.4V to 2.4V. All V DD are 4.75V to 5.25V Parameter t5 Setup to CLK rising t6 Hold from CLK rising WINBOND SYSTEMS LABORATORY Table 6-2. PCI Bus Timing Values ...

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W83C553F Parameter t7 Setup to CLK rising t8 Valid from CLK rising t9 Float from CLK rising WINBOND SYSTEMS LABORATORY Table 6-2 (continued). PCI Bus Timing Values Min Max 10ns - Timing for GNT#. 12ns - Timing for REQ#. 2ns ...

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W83C553F Parameter t11 Address Setup to command low t12 Address hold from command high t13 IDE_IOCHRDY high setup to command high t14 Read data setup to IDE_IOR# high t15 Read data hold from IDE_IOR# high t16 Write data setup to ...

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W83C553F Parameter t20 IDEDRQ[A:B] high to IDEDAK[A:B]# low delay t21 IDEDAK[A:B]# setup to command low t22 CS0#, CS1# setup to command low t23 IDEDAK[A:B]#, CS0#, CS1# hold from command high WINBOND SYSTEMS LABORATORY Table 6-4. IDE Data Transfer Timing Min ...

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W83C553F Parameter t24 IDEIRQ[A:B] high to INT# low or ISA IRQ high t25 IDEIRQ[A:B] low to INT# float or ISA IRQ low t26 RST# low to IDE_RST# low t27 RST# high to IDE_RST# high t28 IDECS1# setup to RST# high ...

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W83C553F 6.2 IDE/ATA Data Transfers This information has been transferred from the ATA-2 x3T9.2 specification for PIO modes 0-3, Multiword DMA modes 0-1 and Single-word DMA modes 0-2. SFF 8033 Rev. 0.2 defines PIO mode 4 and Multiword DMA mode ...

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W83C553F Table 6-6 (continued). PIO ATA Data Transfer Timing Parameter t2 IDEIOR[A:B]# / IDEIOW[A:B]# Mode 0 16-bit t2 Pulse Width 8-bit t2i IDEIOR[A:B]# / IDEIOW[A:B]# Mode 0 recovery time t3 IDEIOW[A:B]# data setup t4 IDEIOW[A:B]# data hold WINBOND SYSTEMS LABORATORY ...

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W83C553F Table 6-6 (continued). PIO ATA Data Transfer Timing Parameter t5 IDEIOR[A:B]# data setup t6 IDEIOR[A:B]# data hold t6z IDEIOR[A:B]# data tri-state t9 IDEIOR[A:B]# / IDEIOW[A:B]# to address valid hold tR Read data valid to IDECHRDY active WINBOND SYSTEMS LABORATORY ...

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W83C553F 6.2.2 Example Single Word DMA ATA Data Transfer Timing Table 6-7. Single Word DMA ATA Data Transfer Timing Parameter t0 Cycle Time tC IDEDAK[A:B]# to IDEDRQ[A:B] delay tD IDEIOR[A:B]# / IDEIOW[A:B]# 16-bit minimum command active time tE IDEIOR[A:B]# data ...

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W83C553F Table 6-7 (continued). Single Word DMA ATA Data Transfer Timing Parameter tF IDEIOR[A:B]# read data hold tG IDEIOW[A:B]# write data setup tH IDEIOW[A:B]# write data hold tI IDEDAK[A:B]# to IDEIOR[A:B]# / IDEIOW[A:B]# setup tJ IDEIOR[A:B]# / IDEIOW[A:B]# to IDEDAK[A:B]# ...

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W83C553F 6.2.3 Example Multiword DMA ATA Data Transfer Timing Table 6-8. Multiword DMA ATA Data Transfer Timing Parameter t0 Cycle Time tC IDEDAK[A:B]# to IDEDRQ[A:B] delay tD IDEIOR[A:B]# / IDEIOW[A:B]# 16-bit minimum command active time WINBOND SYSTEMS LABORATORY Values Min ...

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W83C553F Table 6-8 (continued). Multiword DMA ATA Data Transfer Timing Parameter tE IDEIOR[A:B]# data access tF IDEIOR[A:B]# read data hold tZ IDEDAK[A:B]# to tri-state tG IDEIOR[A:B]# / IDEIOW[A:B]# data setup tH IDEIOR[A:B]# / IDEIOW[A:B]# write data hold WINBOND SYSTEMS LABORATORY ...

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W83C553F Table 6-8 (continued). Multiword DMA ATA Data Transfer Timing Parameter tI IDEDAK[A:B]# to IDEIOR[A:B]# / IDEIOW[A:B]# setup tJ IDEIOR[A:B]# / IDEIOW[A:B]# to IDEDAK[A:B]# hold tKr IDEIOR[A:B]# negated pulse width tKw IDEIOW[A:B]# negated pulse width tLr IDEIOR[A:B]# to IDEDRQ[A:B] delay ...

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W83C553F 6.3 ISA Bus Timing WINBOND SYSTEMS LABORATORY Table 6-9. ISA Master Write to PCI Timing Diagrams 151 ...

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W83C553F WINBOND SYSTEMS LABORATORY Table 6-10. ISA Master Read from PCI Timing Diagrams 152 ...

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W83C553F 7.0 MECHANICAL DESCRIPTION This chapter shows the dimensions of the W83C553F Enhanced SIO with PCI Arbiter chip. 208L QFP (28X28 mm footprint 2.6mm) 208 See Detail F Seating Plane Symbol WINBOND SYSTEMS LABORATORY H D ...

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W83C553F 8.0 Thermal Information Theta JA = Thermal Resistance between Junction and Ambient for the 208PQFP. 0 Theta JA = 43.13 C/W (air velocity = 0 M/s) 0 35.25 C/W(air velocity = 1 M/s) 0 30.90 C/W (air velocity = ...

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W83C553F Driving capacity of output and input/output pins of 553F (Revision G) Pin Name A20M#/PCIRST# 22 AD[31:0] 29-31, 33-37, 41-44, 46, 47, 49, 50, 62-67, 69, 71, 73-79, 81 C/BE[3:0]# 39, 51, 61, 72 PAR 60 FRAME# 53 PERR# 58 ...

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W83C553F IOCHRDY 135 BALE 168 AEN 136 TC 166 DAK[2:0] 194, 192, 195 PMACT#/ISARST 5 SD[15:0] 208-204, 202, 199, 197, 123, 125, 126, 128-131, 133 SECURITY/XDR# 116 XOE# 117 XCS0/ROMCS 119 XCS1/X8XCS 118 INT 10 NMI 11 INIT 3 SPKR ...

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