W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 16

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
WINBOND SYSTEMS LABORATORY
Pin Name
IOCHRDY
BALE
AEN
TC
DRQ[7:5, 3:0]
DAK[2:0]
IRQ[15, 14, 12:9,
7:3]
Pin #
135
168
136
166
1,203,198,
191,190,
193,196
194,192,
195
186,188,
183,181,
179,127,
154,157,
159,161,
163
Table 2-5 (Continued). ISA Bus Signals
Input/
Output
Input/
Output
Output
Output
Output
Input
Output
Input
Description
I/O Channel Ready. This signal is used by ISA slaves to extend the
transfer cycle beyond the default ready timer expiration.
Bus Address Latch Enable. This signal indicates that a valid
address is on the bus.
Address Enable. AEN is asserted during DMA cycles to prevent
I/O devices from misinterpreting the cycle as a valid I/O cycle.
Termination Count. This signal is asserted to indicate that a DMA
channel's word count has reached terminal count.
DMA Request. DMA service request from the DMA controllers.
Encoded DMA Acknowledge. The channel number of the
arbitration winner is encoded in binary. An external decoder is
required to generate DACK[7:5, 3:0]#. The inactive value is 100b.
Interrupt Request.
Pin Descriptions
23