W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 22

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
Electrical Specifications
The IDE interface is fully ANSI CAM compliant to the ATA Revision 3.0 and the ATA-2 specifications. Each storage
device on the two ports is individually programmable to select the desired command on and off times to support ATA defined
PIO MODES 0 through 2 and Multiword DMA MODE 0. Also supported are SFF PIO MODES 3, 4 and 5 (proposed) and
Multiword DMA MODES 1 and 2.
The devices supported are ATA compliant hard disks, tape drives, and CD ROMs. The W83C553F is compliant with the
emerging ATAPI Specification.
Two interrupt controllers can handle a total of 15 interrupt channels. IRQ0 is internally connected to OUT0, of the 82C54
counter/timer. Usually an interrupt is generated by the rising edge of IRQ. IRQ8 and IRQ13, however, are fixed to trigger
on the falling edge for direct connection to the real time clock interrupt or Pentium CPU floating point error signal. RX
4D0h and RX4D1h can be programmed to change the IRQs from edge sensitive to level sensitive interrupts. All external
IRQ lines are not internally pulled-up. I/O port and channel definition matches the IBM PC/AT requirement.
Types A, B, F DMA are supported by the W83C553F. Two integrated 82C37A DMA controllers each generate memory
addresses and control signals to transfer information between a peripheral device and memory, without CPU intervention.
Four DMA channels permit 8-bit peripheral device data transfers. Three channels permit 16-bit peripheral device data
transfers. During a DMA or master cycle, the CPU is held and the W83C553F takes control. Both DMA controllers support
scatter/gather transfer capability on all channels and 32-bit addressing.
The W83C553F has two basic operational states: reset and active. The reset state brings all internal logic to a known state,
and configures some chip features. The active state is the normal operating state that allows software to perform chip
configuration, access to the PCI and ISA register sets, and accessing of up to four IDE devices.
3.2
Active State
When active, the W83C553F will monitor all PCI bus cycles and respond to configuration and I/O cycles. The W83C553F
will always respond to configuration cycles when properly addressed but will always respond to I/O cycles, as indicated in
the internal configuration registers.
Configuration cycles are executed anytime the W83C553F IDSEL pin is asserted, a valid command is detected, and AD[1:0]
are "0" during the address phase. Configuration cycles are executed to program the W83C553F internal configuration
register sets. I/O cycles will only be executed when enabled as indicated in the configuration registers. I/O cycles are used to
transfer command/status and data to/from the IDE devices, as well as to program the bus master register set.
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