W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 42

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
When operating as a bus master on the PCI bus, DMA cycles will be executed on the IDE interface. In this mode, once the
BMEN bit of the Bus Master Control Register is set the W83C553F will de-assert the chip selects for that port and respond to
DRQ as defined above. If an interrupt is generated on the IDE interface, it will be delayed for IDE device to memory
transfers until the FIFO is empty (written to memory). The IDEIOW[A:B]#/IDEIOR[A:B]# will be held high and not
asserted (pause) any time that the FIFO is empty/full.
To maximize the PCI bus bandwidth, the bus master FIFO is independent of the PIO FIFOs. It is 64 bytes deep which allows
the W83C553F to burst transfers of 8 double words consistently. This allows the use of the Memory Read Line and Memory
Write And Invalidate commands.
If both ports operate in the bus master mode, they will share the same FIFO and a fairness arbitration will be employed to
guarantee both ports have transfer time slices.
Using this protocol to transfer data relieves the System CPU overhead by 90% typically. This is achieved because the CPU
only needs to send the command to the target IDE device, set up the bus master PRD table, and program the bus master
register set. There will only be one interrupt per command to service, whereas PIO commands require one interrupt per
sector or block of sectors, and the CPU must manually transfer all data.
PCI bus utilization is also reduced by up to 90% over the standard PIO protocol. The bus master core can transfer one sector
of data with less than 6 microseconds of active bus time, regardless of the IDE device transfer rate. The same PIO transfer
requires over 150 microseconds of active bus time, when using a Mode 0 IDE device.
Two interrupt controllers are included in the W83C553F, and are internally cascaded to handle a total of 15 interrupt
channels. IRQ0 is internally connected to OUT0, of the 82C54 counter/timer. Typically, an interrupt is generated by the
rising edge of an IRQ signal. However, IRQ8 and IRQ13 are fixed to trigger on the falling edge, allowing direct connection
to the real time clock interrupt (IRQ8#), or Pentium CPU floating point error signal (FERR#). Also, RX 4D0h and RX 4D1h
can be programmed to change the IRQs from edge sensitive to level sensitive interrupts. All external IRQ lines are internally
pulled-up to eliminate noises on unconnected request pins. I/O port and channel definition matches that of the IBM PC/AT
requirement.
Two 82C37A DMA controllers are integrated into the W83C553F. Each controller is a four channel DMA device,
generating memory addresses and control signals necessary to transfer information between a peripheral device and memory,
without CPU intervention.
The two controllers are cascaded to provide four DMA channels permitting 8-bit peripheral device data transfers. Three
channels permit 16-bit peripheral device data transfers. The I/O port and channel definition matches that of the IBM PC/AT
requirement.
Type A, B and F DMA are supported in the W83C553F. Both DMA controllers support full 32-bit addressing and
scatter/gather transfer capability.
WINBOND SYSTEMS LABORATORY
3.18
3.19
3.20
Bus Master Transfers
82C59A Interrupt Controller
82C37A DMA Controller
Electrical Specifications
49