W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 41

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
Electrical Specifications
3.17
32-Bit Data Transfers
32-bit data transfers are used to reduce system overhead and improve performance. The standard PIO protocol requires the
system CPU to execute an I/O cycle and a memory cycle to move two bytes of data between the IDE device and memory. To
transfer 4 bytes of data would require two I/O cycles and two memory cycles. This can be accomplished with one 32-bit I/O
and one 32-bit memory cycle. This cuts the CPU cycles in half. By enabling read ahead, the IDE read cycles will be
buffered from the PCI bus and execute in parallel with the system memory reads cutting overhead more. Enabling posted
writes will similarly improve write performance.
PCI Bus 32-Bit PIO Write Cycle
IDE Write Cycle with Posted Writes
PCI Bus 32-Bit PIO Read Cycle
IDE Read Cycle with Read Ahead
The two drawings shown above show the relationship
between the PCI bus and the IDE interface.
WINBOND SYSTEMS LABORATORY
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