W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 8

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
WINBOND SYSTEMS LABORATORY
Pin Name
FRAME#
PERR#
IRDY#
TRDY#
DEVSEL#
STOP#
IDSEL
SERR#
Pin #
53
58
54
55
56
57
40
59
Table 2-2 (Continued). PCI Bus Signals
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input
Input/OD System Error. The W83C553F monitors the SERR# pin to generate
Description
Cycle Frame. Indicates the start and duration of an access. It is
asserted to indicate the start of a bus transaction; during which data
transfers continue. When FRAME# is de-asserted, the transaction is
in the final data phase.
PCI Parity Error.
Initiator Ready. Indicates the initiating agent's ability to complete
the current transaction's data phase. It is used jointly with TRDY#.
During a write, it indicates that valid data is present on AD[31:0].
During a read cycle, it indicates the master is prepared to accept
data.
Target Ready. Indicates the target's ability to complete the current
data phase of the transaction. It is used with IRDY#. During a read
cycle, it indicates that valid data is present on AD[31:0]. During a
write cycle, it indicates the target is prepared to accept data.
Device Select. This signal is asserted by the W83C553F when it is
acting as a target in a transaction. It is an input when the W83C553F
is acting as the initiator of a transaction.
Stop. This is asserted to terminate the current transaction. It causes a
disconnect condition, limiting slave I/O cycles to one data transfer
since I/O burst transfers are not supported. During master cycles, it
indicates the target wants to terminate the cycle.
Initialization Device Select. Chip select signal, used during PCI
configuration read and write cycles.
an NMI if enabled.
Pin Descriptions
15