W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 25

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W83C553FY-G

Manufacturer Part Number
W83C553FY-G
Description
Manufacturer
Nuvoton Technology Corporation of America
Datasheet

Specifications of W83C553FY-G

Lead Free Status / RoHS Status
Compliant

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W83C553F
The next rising clock edge identifies the beginning of the data phase. Address parity is valid and will be checked or ignored
depending on the state of the SE bit of the Device Control Register. The data phase can last one or more clock cycles. Data
will be transferred on the rising clock edge when both IRDY# and TRDY# are asserted. Data parity will be generated (slave
I/O read or bus master memory write cycle) or checked (slave I/O write or bus master memory read cycle) on the next
rising clock edge. The W83C553F will report data parity errors on slave I/O write cycles it claims (by the assertion of
DEVSEL#) and bus master memory write cycles via the PERR# signal when enabled.
Normally for I/O cycles FRAME# will be de-asserted when IRDY# is asserted to signify that this is the last data transfer of
the data phase. STOP# will also be asserted with TRDY# to prevent I/O bursting. Multiple data phases (data bursting) are
supported when operating as a bus master.
WINBOND SYSTEMS LABORATORY
C/BE[3:0]# PCI Bus Cycle
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
Table 3-2 PCI Bus Cycles
Slave Mode
Supported
Supported
Supported
Supported
Ignored
Ignored
Supported
Supported
Ignored
Ignored
Supported
Supported
Supported (aliased to Memory Read)
Ignored
Supported (aliased to Memory Read)
Supported (aliased to Memory Write)
Electrical Specifications
Master Mode
Not Generated
Not Generated
Not Generated
Not Generated
Not Generated
Not Generated
Supported
Supported
Not Generated
Not Generated
Not Generated
Not Generated
Supported
Not Generated
Supported
Supported
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