W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 143

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
tI
tJ
tKr IDEIOR[A:B]# negated
tKw IDEIOW[A:B]# negated
tLr IDEIOR[A:B]# to
tLw
WINBOND SYSTEMS LABORATORY
IDEDAK[A:B]# to
IDEIOR[A:B]# /
IDEIOW[A:B]#
setup
IDEIOR[A:B]# /
IDEIOW[A:B]# to
IDEDAK[A:B]#
hold
pulse width
pulse width
IDEDRQ[A:B] delay
IDEIOW[A:B]# to
IDEDRQ[A:B] delay
Parameter
Table 6-8 (continued). Multiword DMA ATA Data Transfer Timing
Mode 0
Mode 1
Mode 2
Mode 3
Mode 0
Mode 1
Mode 2
Mode 3
Mode 0
Mode 1
Mode 2
Mode 3
Mode 0
Mode 1
Mode 2
Mode 3
Mode 0
Mode 1
Mode 2
Mode 3
Mode 0
Mode 1
Mode 2
Mode 3
Min
0ns
0ns
0ns
20ns
5ns
5ns
50ns
50ns
25ns
215ns
50ns
25ns
Values
120ns
40ns
35ns
40ns
40ns
35ns
Max
The delay from DIOR# or DIOW# until the
state of IORDY is first sampled. If IORDY
is inactive, then the host shall wait until
IORDY is active before the PIO cycle can be
completed. If the device is not driving
IORDY negated at the time tA after the
activation of DIOR# or DIOW#, then t5
shall be met and tRD is not applicable. If
the device is driving IORDY negated at the
time tA after the activation of DIOR# or
DIOW#, then tRD shall be met and t5 is not
applicable.
Notes
Timing Diagrams
150