W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 114

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
Base Address Registers 0 through 3 (10h-13h, 14h-17h, 18h-1Bh, 1Ch-1Fh)
The W83C553F can be configured to support these Base Address Registers or to disable them. This can be useful in
configuring the device to operate in PCI systems that have various levels of configuration compatibility. Base Address
Registers 0 and 1 are used to control the primary IDE port I/O address locations. Base Address Registers 2 and 3 are used to
control the secondary IDE port I/O address locations. IOR[A:B]# and IOW[A:B]# are used with IDECS0# and IDECS1# to
access the primary and second ports. Note: A Base Address register does not contain a valid address when it is equal to "0".
When P0N/L# bit in Programming Interface Register is set, Base Address Register 0,1 can be programmed for relocation to
any address within the 32 bit PCI I/O address space.
When P1N/L# bit in Programming Interface Register is set, Base Address Register 2,3 can be programmed for relocation to
any address within the 32 bit PCI I/O address space.
When relocating the IDE ports, the normal procedure is to first program the Base Address Register with a value of FF FF FF
FFh. Next the register is read. Base Address Registers 0 and 2 will respond with a value of FF FF FF F9h indicating a
decode range of 8 bytes in I/O space, while 1 and 3 will respond with a value of FF FF FF FDh indicating a decode range of 4
bytes in I/O space. Although Base Address Registers 1 and 3 indicate a decode of 4 bytes, they will only claim cycles to byte
lane 2 (of 0 through 3) of the 4 byte range. This means that register accesses to 3F4h, 3F5h, 3F7h, 374h, 375h or 377h (or the
equivalent offset) will not be claimed or executed.
The W83C553F will only decode IDE port addresses if the IOEN bit of the Device Control Register is high and the IDE port
is enabled in the W83C553F function 1: IDE Control/Status Registers.
WINBOND SYSTEMS LABORATORY
The default values of all the registers are located above.
Register
Address
Base
0
1
2
3
1F0h-1F7h
170h-177h
Address
Decode
3F6h
376h
Table 4-3. Base Address Register Mapping
IDE Chip
Select
IDE_CS0#
IDE_CS1#
IDE_CS0#
IDE_CS1#
Default When
00 00 01 F1h
00 00 03 F5h
00 00 01 71h
00 00 03 75h
Enabled
Value When
Programmed
FF FF FF FFh
FF FF FF FDh
FF FF FF F9h
FF FF FF FDh
Electrical Specifications
FF FF FF F9h
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