W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 12

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
WINBOND SYSTEMS LABORATORY
Pin Name
IDECS0#
IDECS1#/
NAT/LEG#
IDEIOWA#
IDEIORA#
IDEIOWB#
IDEIORB#
Pin #
87
86
85
83
84
82
Table 2-4. IDE Interface Bus Signals
Input/
Output
Output
Input/
Output
Output
Output
Output
Output
Description
Drive Chip Select 0. This signal is decoded from the AD bus to
select both primary and secondary IDE Port Command Block
Registers.
Drive Chip Select 1. This signal is decoded from the AD bus to
select both primary and secondary IDE Port Auxiliary Registers.
Native or Legacy Mode Select. During reset, this pin is sampled as
an input to set the Native or Legacy mode of the bus master IDE
controller (Function 1). A high selects Native mode and a low
selects Legacy mode.
Drive I/O Write A. This signal is used jointly with IDECS0# and
IDECS1#. The rising edge of IDEIOWA# latches data into the
primary port IDE device.
Drive I/O Read A. This signal is used jointly with IDECS0# and
IDECS1#. The falling edge of IDEIORA# enables data from the
primary port IDE device. The data is latched internally on the rising
edge of IDEIORA#.
Drive I/O Write B. This signal is used jointly with IDECS0# and
IDECS1#. The rising edge of IDEIOWB# latches data into the
secondary port IDE device.
Drive I/O Read B. This signal is used jointly with IDECS0# and
IDECS1#. The falling edge of the IDEIORB# enables data from the
secondary port IDE device. The data is latched internally on the
rising edge of IDEIORB#.
Pin Descriptions
19