W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 14

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
WINBOND SYSTEMS LABORATORY
Pin Name
BCLK
OSC
LA[23:17]
SA[16:0]
MASTER#
REFRESH#
MEMR#
MEMW#
Pin #
200
172
176,178,
180,182,
184,187,
189
144,145,
147-149,
151,152,
155,158,
160,162,
164,165,
167,169,
171,173
143
150
141
142
Input/
Output
Output
Input
Input/
Output
Input/
Output
Input
Input/
Output
Input/
Output
Input/
Output
Table 2-5. ISA Bus Signals
Description
ISA Bus Clock.
Oscillator. 14 MHz input for generating the internal timer clock.
Latchable Address. The current bus owner drives LA[23:17] to
provide 16M of memory space.
System Address. SA[16:0] provides the 17 least significant address
bits for memory accesses and SA[15:0] provides the entire 16
address bits for I/O accesses.
ISA Master. Master control signal from the ISA bus.
ISA DRAM Refresh Control. This pin is an open drain output and
allows other masters to initiate refresh requests.
Memory Read. Acts as an output during PCI master and DMA
cycles and as an input during ISA master cycles.
Memory Write. Acts as an output during PCI master and DMA
cycles and as an input during ISA master cycles.
Pin Descriptions
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