W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 115

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
Electrical Specifications
Base Address Register 4 (20h-23h)
This Base Address Register is used to define the I/O address of the Bus Master IDE Register set in systems which use multi-
word DMA mode disk drives. This register set is internal to the W83C553F but is located in the I/O address space instead of
the Configuration address space. The default value of Base Address Register 4 is 00000001h. When programmed with a
value of FFFFFFFFh, a value of FFFFFFF1h will be read back indicating a required address range of 16 bytes. The Bus
Master IDE Register set can be located anywhere in the 32 bit I/O address space. Since address 00 00 00 00h is the address
of the motherboard DMA controller, no cycles will be claimed until Base Address Register 4 is programmed to a non-zero
address and IOEN is set in the Device Control Register. The lower 4 bits are hardwired to a value of 1h. Note: A Base
Address register does not contain a valid address when it is equal to "0".
Interrupt Line Register (3Ch)
The Interrupt Line register is an 8-bit register used to communicate interrupt line routing information. This register is
read/write. The POST software is expected to write the appropriate routing information into this register as it initializes and
configures the system. At reset, this register is set to 0Eh to indicate the desired interrupt path to the interrupt controller is
through IRQ14.
Interrupt Pin Register (3Dh)
The Interrupt Pin register is an 8-bit register that defines which interrupt pin the device uses. A value of 01h is hardwired to
this register to signify that INTA# is being used. This interrupt may be a PCI interrupt or an ISA interrupt (i.e. IRQ14).
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