W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 107

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
WINBOND SYSTEMS LABORATORY
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
MWIEN. When this bit is 1b, Memory write and invalidate commands are enabled, when acting
as a bus master. When this bit is 0b, only memory writes can be used. This bit is a 0b after a
reset.
This bit is not used and is hardwired to a logic 0.
BMEN. This bit must be set to allow the W83C553F to perform bus master cycles. Writing a 1b
to this bit will set it. Also, writing a 1b to bit 0 (Start/Stop Bus Master) of the Primary or
Secondary Bus Master IDE Command Register will set this bit. This bit is a 0b after a reset.
This bit is not used and is hardwired to a logic 0b.
IOEN. When bit 0 is set to a 1b, IDE I/O address decodes, based on the W83C553F's
configuration, are enabled. Primary and/or secondary port I/O addresses are decoded if they
are also enabled in the IDE Control/Status Register. They will be the default address range,
unless the Base Address Registers are enabled and programmed. In this case, the Base
Address Registers determine the addresses to be decoded.
Electrical Specifications
114