W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 45

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
The W83C553F SIO controller with PCI arbiter is a multi-function PCI device. Function 0 is the ISA bridge, and Function 1
is the bus master IDE controller. The registers summarized in this section are organized as follows:
Each function of the W83C553F SIO chip supports a complete set of configuration registers as defined in the PCI Spec. Rev.
2.1 for a 32-bit bus implementation. Additional configuration registers are supported for bus master and IDE port/device
control. They can be accessed whenever the PCIRST# signal is de-asserted. These registers are internal to the W83C553F,
and control the operation of the chip when responding to bus I/O cycles.
They are accessed when a configuration bus cycle is executed with IDSEL asserted and AD[1:0] both low. All registers are
implemented as 32-bit registers and the C/BE[3:0]# inputs determine which byte lanes are read/written. This allows the
registers to be accessed 8, 16, 24, or 32 bits at a time. The specific 32-bit register is directly addressed by AD[7:2].
All reserved bits and bytes return a logic 0 when read. All reserved bytes written will execute normal PCI cycles, but will not
affect the operation or device registers.
The internal register information for the W83C553F is organized as follows:
WINBOND SYSTEMS LABORATORY
4.0 REGISTER INFORMATION
•
•
•
•
•
•
•
PCI Configuration Space - ISA Bridge Registers (Function 0)
ISA Bridge (Function 0) I/O Registers
PCI Configuration Space - Bus Master IDE Registers (Function 1)
Bus Master IDE (Function 1) I/O Registers
Register name and Index value offset from base address.
Type (Read and/or Write).
Bit description.
Electrical Specifications
52