W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 106

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
Device Control Register (default = 0000h)
Function:
Type:
Bit Description:
WINBOND SYSTEMS LABORATORY
Bit [15:9]:
Bit 8:
Bit 7:
Bit 6:
Bit 5:
Read/Write
The Device Control Register provides coarse control over the device's ability to generate and respond to
I/O cycles. Since the default value disables the IO decode, it must be programmed by the BIOS/Firmware
to enable this function.
These bits are reserved and hardwired to a logic 0b.
SERR. When this bit is 1b, the SERR# output driver is enabled. A system error will only be
reported for address parity errors. Bit 6 PARITY must also be enabled, or no error will be
reported. Bit 8 is a 0b after a reset.
This bit is not used and is hardwired to a logic 0b.
PARITY. This is the enable bit for the PERR# output driver. When bit 6 is a 1b, slave write data
parity errors, and master memory read data parity errors, will be reported on PERR#. Write
data parity errors are only reported for bus cycles claimed by the W83C553F (DEVSEL#
asserted). Bit 6 is a 0b after a reset.
This bit is not used and is hardwired to a logic 0b.
Electrical Specifications
113