W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 19

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
WINBOND SYSTEMS LABORATORY
FERR#/IRQ13
Pin Name
INT
NMI
INIT
SPKR
PWRGD
IGNNE# /
HRESET#
Pin #
10
11
3
134
2
12
4
Table 2-7. CPU Interface and Miscellaneous Signals
Input/
Output
Output
Output
Output
Output
Input
Input
Output
Description
Interrupt. Interrupt signal from the W83C553F interrupt controller to the
CPU.
Non-Maskable Interrupt.
It functions as Initialize CPU/Software Reset (INIT) when the W83C553F
is in x86 mode, as determined by pin 8 strapping after reset. INIT is
asserted for four PCI clocks following one of these events:
Speaker Data. This output drives an externally buffered speaker.
Power good signal from the power supply. This signal is used to generate
other reset signals to reset the system.
This multi-function pin's default function is Interrupt Request 13 (IRQ13).
The Numerical Co-processor Error (FERR#) function may be enabled by a
bit in the Function 0 PCI Configuration Space AT System Control Register
(Index 4Eh, bit 4).
This multi-function pin functions as Ignore Numeric Error (IGNNE#)
when the W83C553F is in x86 mode as determined by pin 8 strapping after
reset. It functions as HRESET# when the W83C553F is in PowerPC
mode. For connection to the PowerPC, HRESET# is asserted for a
duration of one millisecond after one of the following events:
- Hot Reset bit set (port 92, bit 0)
- CPU Shutdown Cycle
- keyboard Reset Emulation bit is set (bit 1, Index 4E)
- PWRGD active edge
- Hot Reset bit set (port 92, bit 0)
- CPU Shutdown Cycle
- Keyboard Reset Emulation bit is set (bit 1, Index 4E)
Pin Descriptions
26