W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 34

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
Electrical Specifications
3.14
Transaction Termination
The termination of a PCI transaction can be initiated by either the master or target. During termination, the master controls
the completion of all PCI transactions, regardless of what caused the termination. All transactions are concluded when
FRAME# and IRDY# are de-asserted, indicating an IDLE cycle.
When the W83C553F is a bus master, its PCI bus cycles may be terminated by the target as a Disconnect With Data Transfer,
Disconnect Without Data Transfer, or Target Abort. The W83C553F's PCI bus cycles may also be terminated by the
W83C553F itself as a Preemption or a Master Abort.
3.14.1
PCI Disconnect With Data Transfer Timing
The Disconnect With Data Transfer command cycle of Figure 3-9 shows one last data transfer occurring after the target
asserts STOP# to start the termination sequence. The data is still transferred, since IRDY# and TRDY# are asserted. The
W83C553F terminates the current transfer with de-assertion of FRAME#, and the de-assertion of IRDY#, at which point it
releases the bus. The W83C553F will re-request the bus after two clock cycles if more data is to be transferred. The starting
address of the new transfer will be the address of the next untransferred data.
Figure 3-9. Disconnect With Data Transfer Timing
WINBOND SYSTEMS LABORATORY
41