W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 7

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
WINBOND SYSTEMS LABORATORY
Pin Name
PCICLK
A20M# /
PCIRST#
AD[31:0]
C/BE[3:0]#
PAR
Pin #
23
22
29-31,33-37,41-
44, 46,47, 49,
50, 62-67,
69,71,73 -
79,81
39, 51, 61,
72
60
Input/
Output
Input
Output
Input/
Output
Input/
Output
Input/
Output
Table 2-2. PCI Bus Signals
Description
Clock. Provides timing for all transactions on the PCI bus. Also
divides down to generate BCLK.
Address Bit 20 Mask or PCI Reset. This multi-function pin
functions as Address Bit 20 Mask when the W83C553F is in x86
mode, as determined by pin 8 strapping after power-up. It functions
as PCI Reset when the W83C553F is in PowerPC mode. It is driven
for one millisecond duration after one of the following conditions:
PCI Reset is equivalent to ISA Reset logically inverted.
Address or Data. These bits are multiplexed on the same PCI pins.
A valid 32-bit address is available during the address phase with
FRAME# asserted. All subsequent cycles are the data phases.
Bus Command and Byte Enables. These bits are multiplexed on the
same PCI pins. During the address phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase,
C/BE[3:0]# are used for byte enables.
Parity. Even parity across AD[31:0] and C/BE[3:0]#. PAR is valid
one clock after the address phase. For data phases, PAR is valid one
clock after either IRDY# is asserted on the write transaction, or
TRDY# is asserted on a read transaction. PAR remains valid until
one clock after the completion of the current phase. PAR is driven
only for read data phases, and checked during write data phases.
- PWRGD active edge
- Hot Reset is set (port 92, bit 0)
- Reset Drive is set (Clock Divisor Register bit 3)
Pin Descriptions
14