W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 23

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
Four basic data paths are provided. One provides the timing and control functions for 8-bit I/O cycles that communicate
control/status information with the IDE devices. A second data path provides the timing and control functions for 16-bit and
32-bit I/O cycles that are used to transfer data to/from the IDE drives with the PIO protocol. The third is used to access the
internal Configuration and Bus Master IDE Register set. The fourth data path is used for the bus master data transfer
protocol. A block of logic is used to interface to the PCI bus as well as separate 8-bit from 16/32-bit cycles and provide bus
master support. A separate block of logic is used to control the IDE interface and timing as well as control the packing and
unpacking of the data between the IDE buffer logic and the PCI buffer logic.
WINBOND SYSTEMS LABORATORY
3.3
ISA-to-PCI data read
PCI-to-ISA data write
DMA read
DMA write
ISA refresh
Bus Structures
Cycle
PCI address/data->W83C553F
->Latched & ISA addressing
PCI address/data->W83C553F
->Latched & ISA addressing
W83C553F->PCI address/data, W83C553F-
>Latched & ISA address
W83C553F->PCI address/data, W83C553F-
>Latched & ISA address
W83C553F->ISA address
Table 3-1. Address and Data Paths for Basic Cycles
Address Bus Path
ISA data->W83C553F->PCI address/data
PCI address/data->W83C553F
->ISA data
PCI address/data->W83C553F
->ISA data
ISA data->W83C553F->PCI address/data
Electrical Specifications
Data Bus Path
30