W83C553FY-G Nuvoton Technology Corporation of America, W83C553FY-G Datasheet - Page 40

• Manufacturer Part Number: W83C553FY-G
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83C553FY-G

• Lead Free Status / RoHS Status: Compliant

W83C553F
Electrical Specifications
3.16
PIO Transfers
When transferring data with the PIO protocol, I/O read/write cycles are executed on the IDE interface and PIO transfers are
executed on the PCI bus. The IDE interface address and chip select signals will only change when a decoded cycle is
detected on the PCI bus. This minimizes IDE interface switching and EMI noise. Once a 16 or 32 bit cycle to a data port is
detected, the W83C553F will setup the proper address and chip selects. Once the address setup time has been met,
IDEIOR[A:B]# or IDEIOW[A:B]# will be asserted and held on until the on command time has been met. The W83C553F
will then de-assert IDEIOR[A:B]# or IDEIOW[A:B]# and hold the addresses and chip selects stable. If read ahead or posted
writes are enabled for this device, read or write cycles will be executed at the programmed on/off timing until the read ahead
buffer is full, the read ahead count is complete, or the posted write buffer is empty. This will maximize the IDE interface
performance because the address setup and hold timing will only add overhead at the beginning and end of a block transfer.
All timing in between is controlled by the command on/off times or the host throughput which ever is slower. The
IDEIOR[A:B]# / IDEIOW[A:B]# signals will never be asserted (cycle committed) if the FIFO is full/empty.
If an 8 bit cycle to a different register is decoded on the PCI bus while read ahead is active, the read ahead buffer will be
preserved, the read ahead will pause and the 8 bit cycle will be executed. Once the 8 bit cycle is completed the read ahead
will resume if a 16 or 32 bit data port read is decoded on the PCI bus. This allows for the host to check the status register
during a data transfer without loosing data.
If an 8 bit cycle to a different register is decoded on the PCI bus while posted write is active, the posted write buffer will be
written to the IDE device while inserting wait states to the PCI bus. Once the write buffer is empty, the 8 bit cycle will be
executed.
The IDE interface and buffers will not be affected by the W83C553F configuration cycle accesses.
During data port read cycles with read ahead active, if an interrupt is detected on the IDE interface it will not be passed to the
PCI bus until the data buffer is empty.
The 16-byte PIO FIFO allows the two channels to transfer data simultaneously without corrupting data between the channels.
Past dual port chips required that interrupts be disabled during a data transfer because only one data FIFO existed and being
interrupted out of a transfer to access the second port caused the read ahead/posted write data in the FIFO to be lost or
corrupted.
All accesses to configuration registers and all 8 bit IDE accesses will be executed in the real time (read ahead and posted
write not used). Only 16 and 32 bit cycles to an IDE data register will support read ahead or posted writes.
WINBOND SYSTEMS LABORATORY
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