ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 118

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

5.5.2.10 IF Invalidate MSR (IF_INVALIDATE_MSR)
MSR Address
Type
Reset Value
IF_INVALIDATE MSR may be used to invalidate the contents of the Tag RAMs (Level-1 COF cache), Level-0 COF cache,
and the return stack. Devices external to the CPU should issue writes to IF_INVALIDATE_MSR only if the CPU is sus-
pended or stalled.
5.5.2.11 IF Test Address MSR (IF_TEST_ADDR_MSR)
MSR Address
Type
Reset Value
IF_TEST_ADDR_MSR is used to indirectly address the IF state elements, while IF_TEST_DATA_MSR (MSR 0000109h) is
used to read/write the elements. The format of the data written to, or read from IF_TEST_DATA_MSR depends on the value
in IF_TEST_ADDR MSR.
118
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:13
63:2
Bit
Bit
1
0
Name
RSVD
RS
CC
Name
RSVD
00001102h
W
00000000_00000000h
00001108h
R/W
00000000_00000000h
33234H
Description
Reserved.
Invalidate Return Stack.
0: Do not alter the return stack. (Default)
1: Empty the return stack.
Invalidate L0 and L1 COF Cache.
0: Do not alter the COF cache. (Default)
1: Empty the COF cache.
Description
Reserved.
RSVD
IF_TEST_ADDR_MSR Bit Descriptions
IF_INVALIDATE_MSR Bit Descriptions
IF_TEST_ADDR_MSR Register Map
IF_INVALIDATE_MSR Register Map
RSVD
RSVD
RSVD
BLOCK
AMD Geode™ LX Processors Data Book
9
9
8
8
CPU Core Register Descriptions
7
7
6
6
5
5
INDEX
4
4
3
3
2
2
RS CC
1
1
0
0