ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 421

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Video Processor Register Descriptions
6.8.3
6.8.3.1
VP Memory Offset 000h
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:29
23:16
RSVD
15:8
Bit
7:6
28
27
26
25
24
Video Processor Module Control/Configuration Registers
Video Configuration (VCFG)
Name
RSVD (RO)
EN_420
BIT_8_
LINE_SIZE
BIT_9_
LINE_SIZE
SP
INIT_RD_
LN_SIZE
INIT_RD_ADDR
VID_LIN_SIZ
SP
R/W
00000000_00000000h
Description
Reserved (Read Only). Reads back as 0.
Enable 4:2:0 Format.
0: Disable.
1: Enable.
Note: When the input video stream is RGB, this bit must be set to 0.
Bit 8 Line Size. When enabled, this bit increases line size from VID_LIN_SIZ (bits [15:8])
DWORDs by adding 256 DWORDs.
0: Disable.
1: Enable.
Bit 9 Line Size. When enabled, this bit increases line size from {BIT_8_LINE_SIZE,
VID_LIN_SIZ (bits [15:8])} DWORDs by adding 512 DWORDs.
0: Disable.
1: Enable.
Spare. Bit is R/W but has no function.
Increase Initial Buffer Read Address. Increases INIT_RD_ADDR (bits [23:16]) by add-
ing 256 DWORDs to the initial buffer address. (Effectively INIT_RD_ADDR becomes 9
bits (bits [24:16]) of address to the line buffers. Each line buffer location contains 4 pixels.
Therefore INIT_RD_ADDR is restricted to 4 pixel resolution.)
If sub-4 pixel start is desired, use the VP Memory Offset 010h[11:0].
0: Disable.
1: Enable.
Initial Buffer Read Address. This field preloads the starting read address for the line
buffers at the beginning of each display line. It is used for hardware clipping of the video
window at the left edge of the active display. Since each line buffer contains 4 pixels,
INIT_RD_ADDR is restricted to 4 pixel resolution.
For an unclipped window, this value should be 0. For 420 mode, set bits [17:16] to 00.
Video Line Size (in DWORDs). Represents the number of DWORDs that make up the
horizontal size of the source video data.
Spares. Bits are R/W but have not function.
INIT_RD_ADDR
VCFG Bit Descriptions
VCFG Register Map
RSVD
VID_LIN_SIZ
9
8
33234H
7
6
5
4
3
2
1
421
0