ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 457

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Video Processor Register Descriptions
6.8.3.47 Dither RAM Control and Address (DCA)
VP Memory Offset 448h
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit
63:8
0
Bit
5:0
7
6
Name
DENB
Name
RSVD (RO)
A
U
ADDR
R/W
00000000_00000000h
Description
Dithering Enable. Enable/disable dithering. The dither bit must be enabled in order for dither
RAM reads or writes to occur. When this bit is cleared, the internal dither RAM is powered
down, which saves power.
0: Dither disable. The dithering function is turned off. When the dither is disabled the Dithering
1: Dither enable. The dither functions with the number of dither bits as set in the Dithering Bits
Bits Select (bits [3:1]) do not have any effect and the dither RAM is not accessible.
Select (bits [3:1]).
Description
Reserved (Read Only). Reads back as 0.
Dither RAM Access Bit. Allows reads and writes to/from Dither RAM.
0: Disable (do not allow reads or writes).
1: Enable (allow reads and writes).
To perform dither RAM writes and reads, both bits 7 and 6 must be set to 1. In addition
VP Memory Offset 418h bits 12 and 0 must both be set to 1. If any of these bits are not
set to 1, the RAM goes into power-down mode.
Dither RAM Update. This bit works in conjunction with bit 7. If this bit is enabled, it
allows the data to update the RAM.
0: Disable (do not allow dither RAM accesses).
1: Enable (allow dither RAM accesses).
To perform dither RAM writes and reads, both bits 7 and 6 must be set to 1. In addition
VP Memory Offset 418h bits 12 and 0 must both be set to 1. If any of these bits are not
set to 1, the RAM goes into power-down mode.
RAM Address. This 6-bit field specifies the address to be used for the next access to the
dither RAM.
DFC Bit Descriptions (Continued)
RSVD
DCA Bit Descriptions
DCA Register Map
RSVD
9
8
33234H
A
7
U
6
5
4
ADDR
3
2
1
457
0